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ISL22346WFV20Z Folha de dados(PDF) 10 Page - Intersil Corporation |
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ISL22346WFV20Z Folha de dados(HTML) 10 Page - Intersil Corporation |
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10 / 13 page  10 FN6177.0 July 28, 2006 When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi are recalled and loaded into the corresponding WRi to set the wipers to the initial value. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR[6:0]= 7Fh), its wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL22346 is being powered up, all four WRs are reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, all WRs will be reload with the value stored in corresponding non-volatile Initial Value Registers (IVRs). The WRs can be read or written to directly using the I2C serial interface as described in the following sections. The I2C interface Address Byte has to be set to 00h, 01h, 02h or 03h to access the WR of DCP0, DCP1, DCP2 or DCP3 respectively. Memory Description The ISL22346 contains seven non-volatile and five volatile 8-bit registers. The memory map of ISL22346 is on Table 1. The four non-volatile registers (IVRi) at address 0, 1, 2 and 3 contain initial wiper value and volatile registers (WRi) contain current wiper position. In addition, three non-volatile General Purpose registers from address 4 to address 6 are available. The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described below in Table 2. The VOL bit at access control register (ACR[7]) determines whether the access is to wiper registers WRi or initial value registers IVRi. If VOL bit is 0, the non-volatile IVRi registers are accessible. If VOL bit is 1, only the volatile WRi are accessible. Note, value is written to IVRi register also is written to the corresponding WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically OR’d with SHDN pin. When this bit is 0, all DCPs are in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR[5]) is read only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the WRi or ACR while WIP bit is 1. I2C Serial Interface The ISL22346 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL22346 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 16). On power-up of the ISL22346 the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22346 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 16). A START condition is ignored during the power-up of the device. TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 8— ACR 7 Reserved 6 5 4 General Purpose General Purpose General Purpose Not Available Not Available Not Available 3 2 1 0 IVR3 IVR2 IVR1 IVR0 WR3 WR2 WR1 WR0 TABLE 2. ACCESS CONTROL REGISTER (ACR) VOL SHDN WIP 00000 TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE ISL22346 |
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