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FIN24ACGFX Folha de dados(PDF) 1 Page - Fairchild Semiconductor |
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FIN24ACGFX Folha de dados(HTML) 1 Page - Fairchild Semiconductor |
1 / 25 page tm January 2007 © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN24AC Rev. 1.0.3 FIN24AC 22-Bit Bi-Directional Serializer/Deserializer Features ■ Low power for minimum impact on battery life – Multiple power-down modes – AC coupling with DC balance ■ 100nA in standby mode, 5mA typical operating conditions ■ Cable reduction: 25:4 or greater ■ Bi-directional operation 50:7 reduction or greater ■ Differential signaling: – -90dBm EMI when using CTL in lab conditions using a near field probe – Minimized shielding – Minimized EMI filter – Minimum susceptibility to external interference ■ Up to 22 bits in either direction ■ Up to 20MHz parallel interface operation ■ Voltage translation from 1.65V to 3.6V ■ Ultra-small and cost-effective packaging ■ High ESD protection: >8kV HBM ■ Parallel I/O power supply (VDDP) range between 1.65V to 3.6V Applications ■ Micro-controller or pixel interfaces ■ Image sensors ■ Small displays – LCD, cell phone, digital camera, portable gaming, printer, PDA, video camera, automotive General Description The FIN24AC µSerDes™ is a low-power Serializer/ Deserializer (SerDes) that can help minimize the cost and power of transferring wide signal paths. Through the use of serialization, the number of signals transferred from one point to another can be significantly reduced. Typical reduction is 4:1 to 6:1 for unidirectional paths. For bi-directional operation, using half duplex for multiple sources, it is possible to increase the signal reduction to close to 10:1. Through the use of differential signaling, shielding and EMI filters can also be minimized, further reducing the cost of serialization. The differential signal- ing is also important for providing a noise-insensitive sig- nal that can withstand radio and electrical noise sources. Major reduction in power consumption allows minimal impact on battery life in ultra-portable applications. A unique word boundary technique assures that the actual word boundary is identified when the data is deserial- ized. This guarantees that each word is correctly aligned at the deserializer on a word-by-word basis through a unique sequence of clock and data that is not repeated except at the word boundary. A single PLL is adequate for most applications, including bi-directional operation. Ordering Information Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only. µSerDesTM is a trademark of Fairchild Semiconductor Corporation. Order Number Package Number Pb-Free Package Description FIN24ACGFX BGA042 Yes 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide FIN24ACMLX MLP040 Yes 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square |
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