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ATMEGA164P_0702 Folha de dados(PDF) 38 Page - ATMEL Corporation |
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ATMEGA164P_0702 Folha de dados(HTML) 38 Page - ATMEL Corporation |
38 / 408 page 38 8011D–AVR–02/07 ATmega164P/324P/644P When applying an external clock, it is required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes. Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page 38 for details. 7.9 Timer/Counter Oscillator ATmega164P/324P/644P uses the same type of crystal oscillator for Low-frequency Crystal Oscillator and Timer/Counter Oscillator. See ”Low Frequency Crystal Oscillator” on page 34 for details on the oscillator and crystal requirements. The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a exter- nal clock source. See ”Clock Source Connections” on page 31 for details. Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one. See ”The Output Compare Register B contains an 8-bit value that is contin- uously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2B pin.” on page 156 for further description on selecting external clock as input instead of a 32.768 kHz watch crystal. 7.10 Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir- cuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output. 7.11 System Clock Prescaler The ATmega164P/324P/644P has a system clock prescaler, and the system clock can be divided by setting the ”CLKPR – Clock Prescale Register” on page 40. This feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk I/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 7-16 on page 41. When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than Table 7-15. Start-up Times for the External Clock Selection Power Conditions Start-up Time from Power- down and Power-save Additional Delay from Reset (V CC = 5.0V) SUT1..0 BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms 10 Reserved 11 |
Nº de peça semelhante - ATMEGA164P_0702 |
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Descrição semelhante - ATMEGA164P_0702 |
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