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AD5522 Folha de dados(PDF) 9 Page - Analog Devices

Nome de Peças AD5522
Descrição Electrónicos  Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD5522 Folha de dados(HTML) 9 Page - Analog Devices

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Preliminary Technical Data
AD5522
Rev. PrM | Page 9 of 48
TABLE 2. TIMING CHARACTERISTICS
AVDD
10V, AV
SS
≤ −5V, |AV
DD
– AVSS|
20V and 33V, DV
CC
= 2.3V to 5.25V, VREF=5V
(TJ = +25 to +90oC, max specs unless otherwise noted.)
SPI INTERFACE (Figure 5 and Figure 6)
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
595
ns min
Single channel write time
t1
20
ns min
SCLK Cycle Time.
t2
8
ns min
SCLK High Time.
t3
8
ns min
SCLK Low Time.
t4
10
ns min
SYNC Falling Edge to SCLK Falling Edge Setup Time.
t5
15
ns min
Minimum SYNC High Time.
t6
5
ns min
29th SCLK Falling Edge to SYNC Rising Edge.
t7
5
ns min
Data Setup Time.
t8
4.5
ns min
Data Hold Time.
t93
30
ns max
SYNC Rising Edge to BUSY Falling Edge.
t10
BUSY Pulse Width Low
1 DAC X1
1.25
µs max
BUSY Pulse Width Low
2 DAC X1
1.75
µs max
BUSY Pulse Width Low
3 DAC X1
2.25
µs max
BUSY Pulse Width Low
4 DAC X1
2.75
µs max
BUSY Pulse Width Low
Other Regs
270
ns max
BUSY Pulse Width Low, System Control Register/PMU Register/M or C Registers
t11
20
ns min
29th SLCK Falling EDGE to LOAD Falling Edge
t12
20
ns min
LOAD pulse width low
t13
150
ns min
BUSY rising edge to FOH Output Response time
t14
0
ns min
BUSY rising edge to LOAD falling edge
t15
100
ns max
LOAD rising edge to FOH Output Response time
t16
10
ns min
RESET Pulse Width Low.
t17
300
µs max
RESET Time Indicated by BUSY
Low.
t18
100
ns min
Minimum SYNC High Time in Readback Mode.
t194, 5
25
ns max
DVCC = 5V to 5.25V, SCLK Rising Edge to SDO Valid.
45
ns max
DVCC = 3V to 3.7V, SCLK Rising Edge to SDO Valid
60
ns max
DVCC = 2.3V to 3V, SCLK Rising Edge to SDO Valid
LVDS INTERFACE (Figure 7)
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
10
ns min
SCLK Cycle Time.
t2
4
ns min
SCLK Pulse Width High and Low Time.
t3
2
ns min
SYNC to SCLK Setup Time.
t4
2
ns min
Data Setup Time.
t5
2
ns min
Data Hold Time.
t6
2
ns min
SCLK to SYNC Hold Time.
t7
TBD
ns min
SCLK Rising Edge to SDO Valid.
t8
TBD
ns min
SYNC high time
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3 See Figure 5 and Figure 6
4 This is measured with load circuit of Figure 4
5SDO output gets slower with lower DVCC supply and may require use of slower SCLK.


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