TB6560HQ/FG

2006-05-31

9

Relationship between Enable, RESET and Output (OUT and MO)

Ex-1: ENABLE 1-2-Phase Excitation (M1: H, M2: L)

The ENABLE signal at Low level disables only the output signals. Internal logic functions proceed in

accordance with input clock signals and without regard to the ENABLE signal. Therefore output current is

initiated by the timing of the internal logic circuit after release of disable mode.

When the RESET signal goes Low level, output goes Initial state and the MO output goes Low level (Initial

state: A Channel output current is 100%).

Once the RESET signal returns to High level, output continues from the next state after Initial from the

next raise in the Clock signal.

CLK

ENABLE

RESET

MO

100

(%)

0

OFF

71

CW

CLK

ENABLE

RESET

MO

100

(%)

0

71

CW