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TDA1541 Folha de dados(PDF) 8 Page - NXP Semiconductors |
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TDA1541 Folha de dados(HTML) 8 Page - NXP Semiconductors |
8 / 12 page November 1985 8 Philips Semiconductors Product specification Dual 16-bit DAC TDA1541 * Signal-to-noise ratio + THD with 1 kHz full scale sinewave generated at a sampling rate of 176,4 kHz. ** Vripple = 1% of supply voltage and fripple = 100 Hz. Signal -to-noise ratio + THD* S/N 90 95 − dB Settling time to ± 1 LSB tcs − 1 −µs Channel separation α 80 tbf − dB Unbalance between outputs ∆IFS − 0,1 0,2 dB Time delay between outputs td −− 1 µs Power supply ripple rejection** VDD = +5 V RR − tbf − dB VDD1 = −5 V RR − tbf − dB VDD2 = −15 V RR − tbf − dB Signal-to-noise ratio at bipolar zero S/N −−100 − dB Timing (see Figs 3, 4 and 5) Rise time tr −− 35 ns Fall time tf −− 35 ns Bit clock cycle time tCY 160 −− ns Bit clock HIGH time tHB 48 −− ns Bit clock LOW time tLB 48 −− ns Bit clock fall time to latch rise time tFBRL 0 −− ns Bit clock rise time to latch fall time tRBFL 0 −− ns Data set-up time to bit clock tSDB 32 −− ns Data hold time to bit clock tHDB 0 −− ns Data set-up time to system clock tSDS 32 −− ns Word select hold time to system clock tHWS 0 −− ns Word select set-up time to system clock tSWS 32 −− ns Bit clock fall time to system clock rise time tFBRS 32 −− ns System clock rise time to bit clock fall time tRSFB 32 −− ns System clock fall time to bit clock rise time tFSRB 50 −− ns Bit clock rise time to system clock fall time tRBFS 0 −− ns Latch enable LOW time tLLE 20 −− ns Latch enable HIGH time tHLE 32 −− ns PARAMETER SYMBOL MIN. TYP. MAX. UNIT |
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