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LM2506GR Folha de dados(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Nome de Peças LM2506GR
Descrição Electrónicos  Low Power Mobile Pixel Link (MPL) Level 0, 18-bit RGB Display Interface Serializer and Deserializer
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Fabricante Electrônico  NSC [National Semiconductor (TI)]
Página de início  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM2506GR Folha de dados(HTML) 6 Page - National Semiconductor (TI)

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Recommended Input Timing Requirements
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SER PIXEL CLOCK (PCLK)
f
Pixel Clock Frequency
2
13.3
MHz
t
CP
Pixel Clock Period
75.2
500
ns
PCLK
DC
Pixel Clock Duty Cycle
30
50
70
%
t
T
Transition Time
(Note 7)
2
ns
t
STOPpclk
PClock Stop Gap
300
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VDDIO = 1.8V and VDD =VDDA = 1.8V and TA = 25˚C.
Note 3: Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise
specified.
Note 4: MPL Current Threshold is set to be 3XIB by the MPL start up Sequence - this is a functional specification only.
Note 5: Total Supply Current Conditions: RGB Mode, worse case data pattern, 13.3MHz PCLK, DES CL = 15pF, TYP VDDIO =VDDA =VDDcore = 1.8V, MAX VDDIO
= 3.0V, MAX VDDA = VDDcore = 2.0V.
Note 6: Supply Current Conditions: RGB Mode, PRBS case data pattern, 13.3MHz PCLK, DES CL = 15pF, TYP VDDIO =VDDA =VDDcore = 1.8V.
Note 7: Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality.
Note 8: Guaranteed functionally by the IDDZ parameter. See also Figure 8.
Note 9: This is a functional parameter and is guaranteed by design or characterization.
Timing Diagrams
20125516
FIGURE 1. Serial Data Valid — DES Input Set and Hold Time
20125518
FIGURE 2. DES Output Rise and Fall Time (PCLK)
20125529
FIGURE 3. Stop Clock Power Down (SER)
www.national.com
6


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