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M41T60 Folha de dados(PDF) 10 Page - STMicroelectronics |
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M41T60 Folha de dados(HTML) 10 Page - STMicroelectronics |
10 / 24 page Clock operation M41T60 10/24 3 Clock operation The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of 32.768KHz. The accuracy of the Real-Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The eight-byte Clock Register (see Table 2 on page 12) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, Minutes, and Hours are contained within the first three registers. Bits D6 and D7 of Clock Register 05h (Century/Month Register) contain the CENTURY Bit 0 (CB0) and the CENTURY Bit 1 (CB1). See Table 3 on page 14 for additional explanation. Bits D0 through D2 of Register 03h contain the Day (day of the week). Registers 04h, 05h, and 06h contain the Date (day of the month), Century/Month, and Years. the eighth clock register is the Calibration Register (this is described in the Clock Calibration section). Bit D7 of Register 00h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0,' the oscillator restarts within one second (typical). Note: Upon initial power-up, the user should set the ST Bit to a '1,' then immediately reset the ST Bit to '0.' This provides an additional “kick-start” to the oscillator circuit. Bit D7 of Register 01h contains the Oscillator Fail Interrupt Enable Bit (OFIE - see the description in the Oscillator Fail Detection section). Note: A WRITE to ANY location within the first seven bytes of the clock register (0h-6h), including the OFIE and ST Bit, will result in an update of the system clock and a reset of the divider chain. This could result in an inadvertent change of the current time. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The seven Clock Registers may be read one byte at a time, or in a sequential block. The Calibration Register (Address location 7h) may be accessed independently. Provision has been made to ensure that a clock update does not occur while any of the clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. this will prevent a transition of data during the READ. 3.1 Calibrating the clock The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768Hz. The accuracy of the clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. The M41T60 oscillator is designed for use with a 6pF crystal load capacitance. When the Calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C. The oscillation rate of crystals changes with temperature (see Figure 11 on page 12). The M41T60 design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 12 on page 13. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration Bits found in the Calibration Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Bits occupy the five lower-order bits (D4-D0) in the Calibration Register 07h. |
Nº de peça semelhante - M41T60_05 |
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Descrição semelhante - M41T60_05 |
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