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AM29243EH Folha de dados(PDF) 7 Page - Advanced Micro Devices |
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AM29243EH Folha de dados(HTML) 7 Page - Advanced Micro Devices |
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7 / 36 page  P R E L I M I N A R Y 7 Am29240 EH Microcontroller Series ™ KEY FEATURES AND BENEFITS The Am29240EH microcontroller series extends the line of RISC microcontrollers based on 29K family architec- ture, providing performance upgrades to the Am29205 and Am29200 microcontrollers. The RISC microcontrol- ler product line allows users to benefit from the very high performance of the 29K family architecture, while also capitalizing on the very low system cost made possible by integrating processor and peripherals. The Am29240EH microcontroller series expands the price/performance range of systems that can be built with the 29K family. The Am29240EH microcontroller series is fully software compatible with the Am29000, Am29005, Am29030, Am29035, Am29040, and Am29050 microprocessors, as well as the Am29200 and Am29205 microcontrollers. It can be used in exist- ing 29K family microcontroller applications without soft- ware modifications. On-Chip Caches The Am29240EH microcontroller series incorporates a 4-Kbyte, two-way instruction cache that supplies most processor instructions without wait states at the proces- sor frequency. For best performance, the instruction cache supports critical-word-first reloading with fetch- through, so that the processor receives the required instruction and the pipeline restarts with minimum delay. The instruction cache has a valid bit per word to mini- mize the reload overhead. All cache array elements are visible to software for testing and preload. The Am29240EH and Am29243EH microcontrollers in- corporate a 2-Kbyte, two-way set-associative data cache. The data cache appears in the execute stage of the processor pipeline, so that loaded data is available immediately to the next instruction. This provides the maximum performance for loads without requiring load scheduling. This minimizes the time the processor waits on external data as well as minimizing the reload time. The data cache uses a write-through policy with a two- entry write buffer. Byte, half-word, and word reads and writes are supported. All cache array elements are vis- ible to software for testing and preload. Single-Cycle Multiplier The Am29240EH and Am29243EH microcontrollers incorporate a full combinatorial multiplier that accepts two 32-bit input operands and produces a 32-bit result in a single cycle. The multiplier can produce a 64-bit re- sult in two cycles. The multiplier permits maximum per- formance without requiring instruction scheduling, since the latency of the multiply is the same as the la- tency of other integer operations. High-performance multiplication benefits imaging, signal processing, and state modeling applications. Complete Set of Common Peripherals The Am29240EH microcontroller series minimizes sys- tem cost by incorporating a complete set of system facili- ties commonly found in embedded applications, eliminating the cost of additional components. The on- chip functions include: a ROM controller, a DRAM con- troller, a peripheral interface adapter, a DMA controller, a programmable I/O port, a parallel port, up to two serial ports, and an interrupt controller. A video interface is also included in the Am29240EH and Am29245EH mi- crocontrollers for printer, scanner, and other imaging ap- plications. These facilities allow many simple systems to be built using only the Am29240EH microcontroller se- ries, external ROM, and/or DRAM memory. ROM Controller The ROM controller supports four individual banks of ROM or other static memory, each with its own timing characteristics. Each ROM bank may be a different size and may be either 8, 16, or 32 bits wide. The ROM banks can appear as a contiguous memory area of up to 64 Mbytes in size. The ROM controller also supports byte, half-word, and word writes to the ROM memory space for devices such as flash EPROMs and SRAMs. DRAM Controller The DRAM controller supports four separate banks of dynamic memory. Each bank may be a different size and must be 32 bits wide. The DRAM banks can appear as a contiguous memory area of up to 64 Mbytes in size. The DRAM controller supports two- or three-cycle accesses (programmable by software), with single-cycle page- mode and burst-mode accesses. Burst accesses are supported at two initial, one burst, or three initial, one burst. Peripheral Interface Adapter The Peripheral Interface Adapter (PIA) permits glueless interfacing to as many as six external peripheral chips. The PIA allows for additional system features imple- mented by external peripheral chips. DMA Controller The DMA controller provides up to four channels for transferring data between the DRAM and internal or ex- ternal peripherals. Fly-by DMA transfers data directly between an external peripheral and DRAM or ROM, permitting very high data bandwidth. The peripheral must support the timing of the memory (DRAM or ROM). The transfer occurs at the rate of one 32-bit word per cycle, if DRAM page-mode accesses or ROM burst-mode or single-cycle accesses are enabled. For page-mode DRAM, the TDMA signal is asserted on the rising edge following the last access. For an initial access, TDMA is asserted simultaneously with DACKx. DMA wait states and peripheral wait states are ignored |
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