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M41ST85WMX6E Folha de dados(PDF) 10 Page - STMicroelectronics |
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M41ST85WMX6E Folha de dados(HTML) 10 Page - STMicroelectronics |
10 / 34 page M41ST85W 10/34 READ Mode In this mode the master reads the M41ST85W slave after setting the slave address (see Figure 11.). Following the WRITE Mode Control Bit (R/ W=0) and the Acknowledge Bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are re- peated followed by the READ Mode Control Bit (R/ W=1). At this point the master transmitter be- comes the master receiver. The data byte which was addressed will be trans- mitted and the master receiver will send an Ac- knowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41ST85W slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter (see Figure 12., page 11). The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume ei- ther due to a Stop Condition or when the pointer increments to a non-clock or RAM address. Note: This is true both in READ Mode and WRITE Mode. An alternate READ Mode may also be implement- ed whereby the master reads the M41ST85W slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 13., page 11). Figure 11. Slave Address Location AI00602 R/W SLAVE ADDRESS START A 0 100 0 11 |
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