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SN74AHC374DGVRG4 Folha de dados(PDF) 2 Page - Texas Instruments |
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SN74AHC374DGVRG4 Folha de dados(HTML) 2 Page - Texas Instruments |
2 / 22 page SN54AHC374, SN74AHC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS240I – OCTOBER 1995 – REVISED JULY 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L ↑ H H L ↑ LL L H or L X Q0 H X X Z logic diagram (positive logic) OE To Seven Other Channels 1 11 3 2 CLK 1D C1 1D 1Q |
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Descrição semelhante - SN74AHC374DGVRG4 |
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