MC100ES6056

3.3V, 2.5VECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER

ADVANCED CLOCK DRIVERS DEVICES

IDT™ / ICS™ 2:1 MULTIPLEXER

4

MC100ES6056 REV. 5 JULY 16, 2007

Figure 1

Figure 2. Typical Termination for Output Driver and Device Evaluation

1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50

Symbol

Characteristics

–40°C to 85°C

Unit

Min

Typ

Max

Maximum Frequency

> 3

GHz

D to Q, Q

SEL to Q, Q

COM_SEL to Q, Q

300

300

300

400

430

490

500

600

650

ps

ps

ps

Skew

Part-to-Part

2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are

measured from the cross point of the inputs to the cross point of the outputs.

10

50

200

ps

ps

Cycle-to-Cycle Jitter

RMS (1

σ)

1

ps

Minimum Input Swing

200

800

1200

mV

Differential Cross Point Voltage

V

Output Rise/Fall Time (20%–80%)

70

120

230

ps

Driver

Device

Receiver

Device

QD

D

Q

50

Ω

50

Ω