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ML145146-6P Folha de dados(PDF) 9 Page - LANSDALE Semiconductor Inc.

Nome de Peças ML145146-6P
Descrição Electrónicos  4-Bit Data Bus Input PLL Frequency Synthesizer
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Fabricante Electrônico  LANSDALE [LANSDALE Semiconductor Inc.]
Página de início  http://www.lansdale.com
Logo LANSDALE - LANSDALE Semiconductor Inc.

ML145146-6P Folha de dados(HTML) 9 Page - LANSDALE Semiconductor Inc.

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LANSDALE Semiconductor, Inc.
ML145146
www.lansdale.com
Page 9 of 12
Issue 0
RECOMMENDED READING
Technical Note TN–24 Statek Corp.
Technical Note TN–7 Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc. iEEE, Vol 57, No 2 Feb, 1969
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Tecchnology, June 1969
P.J. Ottowitz, “AGuide to Crystal Selection”, Electronic
Design, May 1966
DUAL–MODULUS PRESCALING
The technique of dual–modulus prescaling is well estab-
lished as a method of acheiving high performance frequency
synthesizer operation at high frequencies. Basically, the
approach allows relatively low–frequency programmable coun-
ters to be used as high–frequency programmable counters with
speed capability of several hundred MHz. This is possible
without the sacrifice in system resolution and performance that
results if a fixed (single–modulus) divider is used for the
prescaler.
In dual–modulus prescaling, the lower speed counters must
be uniquely configured. Special control logic is necessary to
select the divide value P or P ÷ 1 in the prescaler for the
required amount of time (see modullus control definition).
Lansdale’s dual–modulus frequency synthesizers contain this
feature and can be used with a variety of dual–modulus
prescalers to allow speed, complexity and cost to be tailored to
the system requirements. Prescalers having P, P ÷ 1 divide val-
ues in the range of ÷3/÷4 to ÷128/÷129 can be controlled by
most Lansdale frequency synthesizers.
Several dual–modulus prescaler approaches suitable for use
with the ML145146 are:
DESIGN GUIDELINES
The system total divide value. Ntotal (NT) will be dictated
by the application. i.e.,
N is the number programmed into the ÷N counter, A is the
number programmed into the ÷A counter, P and P ÷ 1 are the
two selectable divide ratios available in the dual–modulus
prescalers. To have a range of NT values in sequence, the ÷A
counter is programmed from zero through P ÷ 1 for a particu-
lar value N in the ÷N counter. N is then incremented to the N
÷ 1, and the ÷A is sequenced from 0 through P ÷ 1 again.
There are minimum and maximum values that can be
achieved for NT. These values are a function of P and the size
of the ÷N and ÷A counters. The constraint N
≥ A always
applies. If Amax = P – 1, then Nmin ≥ P – 1. Then NTmin =
(P – 1) P + A or (P – 1)P since A is free to assume the value of 0.
NTmax ÷Nmax • P + Amax
To maximize system frequency capability, the dual–modulus
prescaler output must go from low to high after each group of
P or P – 1 input cycles. The prescaler should divide by P when
its modulus control line is high and by P – 1 when the modulus
control is low.
For the maximum frequency into the prescaler (fVCOmax),
the value used for P must be large enough such that:
1. fVCO max divided by P may not exceed the frequency
capability of fin (input to the ÷N and ÷A counters).
2. The period of fVCO divided by P must be greater than the
sum of the times:
a. Propagation delay through the dual modulus
prescaler.
b. Prescaler setup or release time relative to its modulus
control signal.
c. Propagation time from fin to the modulus control
output for the frequency synthesizer device.
A sometimes useful simplification in the programming code
can be achieved by choosing the values for P of 8, 16, 32, or
64. For these cases, the desired value of NT results when NT
in binary is used as the program code to the ÷N and ÷A coun-
ters treated in the following manner:
1.
Assume the ÷A counter contains “a” bits where 2a
≥P.
2.
Always program all higher order ÷A counter bits
above “a” to 0
3.
Assume the ÷N counter and the ÷A counter (with all
the higher order bits above “a” ignored) combined
into a single binary counter of n + a bits in length (n =
number of divider stages in the ÷N counter). The
MSB of this “hypothetical” counter is to correspond to
the MSB of ÷N and the LSB is to correspond to the
LSB of ÷A. The system divide value, NT, now results
when the value of NT in binary is used to program
the “new” n + a bit counter.
By using the two devices, several dual–modulus values are
achievable (shown in Figure 11).
ML12009
ML12011
ML12013
ML12015
ML12016
ML12017
ML12018
ML12032
440 MHz
500 MHz
500 MHz
225 MHz
225 MHz
225 MHz
520 MHz
1.1 GHz
÷5/÷6
÷8/÷9
÷10/÷11
÷32/÷33
÷40/÷41
÷64/÷65
÷128/÷129
÷64/65 or ÷128/129


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