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ADV7403BSTZ-110 Folha de dados(PDF) 7 Page - Analog Devices

Nome de Peças ADV7403BSTZ-110
Descrição Electrónicos  12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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ADV7403
Rev. SpA | Page 7 of 24
TIMING CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.
Table 3.
Parameter1, ,
2 3
Symbol
Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
28.63636
MHz
Crystal Frequency Stability
±50
ppm
Horizontal Sync Input Frequency
14.8
110
kHz
LLC1 Frequency Range4
12.825
140
MHz
I2C PORT5
SCLK Frequency
400
kHz
SCLK Min Pulse Width High
t1
0.6
μs
SCLK Min Pulse Width Low
t2
1.3
μs
Hold Time (Start Condition)
t3
0.6
μs
Setup Time (Start Condition)
t4
0.6
μs
SDA Setup Time
t5
100
ns
SCLK and SDA Rise Time
t6
300
ns
SCLK and SDA Fall Time
t7
300
ns
Setup Time for Stop Condition
t8
0.6
μs
RESET FEATURE
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC1 Mark Space Ratio
t9:t10
45:55
55:45
% duty
cycle
DATA and CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)6
t11
Negative clock edge to start of
valid data
3.6
ns
Data Output Transition Time SDR (SDP)6
t12
End of valid data to negative
clock edge
2.4
ns
Data Output Transition Time SDR (CP)7
t13
End of valid data to negative
clock edge
2.8
ns
Data Output Transition Time SDR (CP)7
t14
Negative clock edge to start of
valid data
0.1
ns
Data Output Transition Time DDR (CP)7, 8
t15
Positive clock edge to end of
valid data
−4 + TLLC1/4
ns
Data Output Transition Time DDR (CP)7, 8
t16
Positive clock edge to start of
valid data
0.25 + TLLC1/4
ns
Data Output Transition Time DDR (CP)7, 8
t17
Negative clock edge to end of
valid data
−2.95 + TLLC1/4
ns
Data Output Transition Time DDR (CP)7, 8
t18
Negative clock edge to start of
valid data
−0.5 + TLLC1/4
ns
DATA and CONTROL INPUTS5
Input Setup Time (Digital Input Port)
t19
HS_IN, VS_IN
9
ns
DE_IN, data inputs
2.2
ns
Input Hold Time (Digital Input Port)
t20
HS_IN, VS_IN
7
ns
DE_IN, data inputs
2
ns
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).
3 Guaranteed by characterization.
4 Maximum LLC1 frequency is 110 MHz for ADV7403BSTZ-110.
5 TTL input values are 0 V to 3 V, with rise/fall times ≥3 ns, measured between the 10% and 90% points.
6 SDP timing figures obtained using default drive strength value (0xD5) in register subaddress 0xF4.
7 CP timing figures obtained using max drive strength value (0xFF) in Register Subaddress 0xF4.
8 DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.


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