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TMP1942XBG Folha de dados(PDF) 10 Page - Toshiba Semiconductor |
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TMP1942XBG Folha de dados(HTML) 10 Page - Toshiba Semiconductor |
10 / 106 page TMP1942FD TMP1942FD-9 2.2 Pin Usage Information Table 2.2.1 lists the input and output pins of the TMP1942FD, including alternate pin names and functions for multi-function pins. Table 2.2.1 Pin Names and Functions Pin Name # of Pins Type Function P00-P07 AD0-AD7 8 Input/Output Input/Output Port 0: Individually programmable as input or output Address (Lower): Bits0-7 of the address/data bus P10-P17 AD8-AD15 A8-A15 8 Input/Output Input/Output Output Port 1: Individually programmable as input or output Address/Data (Upper): Bits 8-15 of the address/data bus Address: Bits 8-15 of the address bus P20-P27 A0-A7 A16-A23 8 Input/Output Output Output Port 2: Individually programmable as input or output Address: Bits 0-7 of the address bus Address: Bits 16-23 of the address bus P30 RD 1 Output Output Port 30: Output-only Read Strobe: Asserted during a read operation from an external memory device P31 WR 1 Output Output Port 31: Output-only Write Strobe: Asserted during a write operation on D0-D7 P32 HWR 1 Input/Output Output Port 32: Programmable as input or output (with internal pull-up resistor) Higher Write Strobe: Asserted during a write operation on D8-D15 P33 WAIT 1 Input/Output Input Port 33: Programmable as input or output (with internal pull-up resistor) Wait: Causes the CPU to suspend external bus activity P34 BUSRQ 1 Input/Output Input Port 34: Programmable as input or output (with internal pull-up resistor) Bus Request: Asserted by an external bus master to request bus mastership P35 BUSAK 1 Input/Output Output Port 35: Programmable as input or output (with internal pull-up resistor) Bus Acknowledge: Indicates that the CPU has relinquished the bus in response to BUSRQ P36 W / R 1 Input/Output Output Port 36: Programmable as input or output (with internal pull-up resistor) Read/Write: Indicates the direction of data transfer on the bus: 1 = read or dummy cycle, 0 = write cycle P37 DSU 1 Input/Output Input Port 37: Programmable as input or output (with internal pull-up resistor) DSU enable signal: DSU is enabled when this pin is sampled low at the rising edge of RESET . To enable DSU, this pin should be pulled down. (Flash version only) P40 0 CS 1 Input/Output Output Port 40: Programmable as input or output (with internal pull-up resistor) Chip Select 0: Asserted low to enable external devices at programmed addresses P41 1 CS 1 Input/Output Output Port 41: Programmable as input or output (with internal pull-up resistor) Chip Select 1: Asserted low to enable external devices at programmed addresses P42 2 CS 1 Input/Output Output Port 42: Programmable as input or output (with internal pull-up resistor) Chip Select 2: Asserted low to enable external devices at programmed addresses P43 3 CS 1 Input/Output Output Port 43: Programmable as input or output (with internal pull-up resistor) Chip Select 3: Asserted low to enable external devices at programmed addresses P44 SCOUT 1 Input/Output Output Port 44: Programmable as input or output System Clock Output: Drives out a clock signal at the same frequency as the CPU clock (high-speed or low-speed) P50-P57 AN0-AN7 ADTRG 8 Input Input Input Port 5: Input-only Analog Input: Input to the on-chip A/D converter External A/D trigger pin for starting an A/D conversion (multiplexed with P57) P60-P67 AN8-AN15 KEY0-KEY7 1 Input/Output Input Input Port 6: Input-only Analog Input: Input to the on-chip A/D converter Key-On Wakeup Input (dynamic pull-up selectable) (with internal pull-up resistor) P90 DSU (DCLK) KEY8 1 Input/Output Output Input Port 90: Programmable as input or output DSU pin Key-On Wakeup Input (dynamic pull-up selectable) (with internal pull-up resistor) P91 DSU (PCST2) KEY9 1 Input/Output Output Input Port 91: Programmable as input or output DSU pin Key-On Wakeup Input (dynamic pull-up selectable) (with internal pull-up resistor) |
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