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TMP1962C10BXBG Folha de dados(PDF) 2 Page - Toshiba Semiconductor |
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TMP1962C10BXBG Folha de dados(HTML) 2 Page - Toshiba Semiconductor |
2 / 459 page TMP1962C10BXBG 2006-02-21 TMP1962-2 • On-chip high-speed memory • DSP function: Executes 32-bit x 32-bit multiplier operations with a 64-bit accumulation in a single clock cycle. • Low power consumption • Optimized design using a low-power cell library • Programmable standby modes in which processor clocks are stopped 3) Fast interrupt response suitable for real-time control • Distinct starting locations for each interrupt service routine • Automatically generated vectors for each interrupt source • Automatic updates of the interrupt mask level (2) On-chip program memory and data memory Product On-Chip ROM On-Chip RAM TMP1962C10AXB 1 Mbyte 40 Kbyte TMP1962F10AXB 1 Mbyte (Flash) 40 Kbyte • ROM correction logic (8 words x 8 blocks) (3) External memory expansion • 16-Mbyte off-chip address space for code and data • External data bus Separate bus/multiplexed bus: Dynamic bus sizing for 8-bit and 16-bit data ports (4) 8-channel DMA controller • Interrupt- or software-triggered • Transfer destination: On-chip memory, on-chip peripherals, external memory, external peripherals (5) 12-channel 8-bit timer • 8/16/24/32-Bit Interval Timer mode • 8-Bit PWM mode • 8-Bit PPG mode (6) 4-channel 16-bit timer • 16-Bit Interval Timer mode • 16-Bit Event Counter mode • 16-bit PPG output • Input capture • 2-phase pulse input counter (2 channels) |
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