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AD5329KRM-REEL7 Folha de dados(PDF) 2 Page - Analog Devices

Nome de Peças AD5329KRM-REEL7
Descrição Electrónicos  Two?셲 Complement Dual, 12-Bit DACs
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD5329KRM-REEL7 Folha de dados(HTML) 2 Page - Analog Devices

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AD5329 -- SPECIFICATIONS
REV PrC 20 DEC 99
– 2 –
Information contained in this Preliminary Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present
form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 562-7254; FAX 408 562-7154; email; walt.heinzer@analog.com
ELECTRICAL CHARACTERISTICS (VDD = +5V±10%, 0°C < TA < +70°C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
DC CHARACTERISTICS
Resolution
N
12
Bits
Differential Nonlinearity Error
DNL
–1
±0.5
+1
LSB
Integral Nonlinearity Error
INL
–0.05
±0.02
+0.05
%FS
Integral Nonlinearity Error
INL
Within 256 codes of VBZ
–0.02
±0.01
+0.02
%FS
Full-Scale Temperature Coefficient2
∆VFS/∆T
Code = 7FFH
100
ppm/°C
Positive-Full-Scale Error
V+FSE
Code = 7FFH
–0.1
-0.05
+0.1
%FS
Bipolar-Zero-Scale Error
VBZSE
Code = 000H
–0.1
+0.1
+0.1
V
Negative-Full-Scale Error
V-FSE
Code = 800H
–0.1
-0.05
+0.1
%FS
ANALOG OUTPUTS
Nominal Positive Full-Scale
VOUTA/B
Code = 7FFH
4
Volts
Positive Full-Scale Tempco2
TCVOUTA/B
Code = 7FFH
±100
ppm/°C
Nominal VBZ Output Voltage
VBZ
2
Volts
Bipolar-Zero Output Resistance2
RBZ
1
Ohm
Nominal Peak-Peak Output Swing
|V+FS| + |V-FS| Code 7FFH to Code 800H
4
Volts
DIGITAL INPUTS
Input Logic High
VIH
VDD = +5V
2.4
V
Input Logic Low
VIL
VDD = +5V
0.8
V
Input Current
IIL
VIN = 0V or +5V, VDD = +5V
±1
µA
Input Capacitance2
CIL
5
pF
POWER SUPPLIES
Power Supply Range
VDD Range
4.5
5.5
V
Supply Current
IDD
VIH = VDD or VIL = 0V
2.5
mA
Supply Current in Shutdown
IDD_SHDN
VIH = VDD or VIL = 0V, B14=0
40
µA
Power Dissipation3
PDISS
VIH = VDD or VIL = 0V, VDD = +5.5V
12.5
mW
Power Supply Sensitivity
PSS
∆VDD = +5V ±10%
0.0002
0.01
%/%
DYNAMIC CHARACTERISTICS2
Settling Time
tS
For a 16 LSB step change
2
3
µs
INTERFACE TIMING CHARACTERISTICS2,4
SCLK Clock Cycle time
t 1
35
ns
Input Clock Pulse Width
t 2, t 3
Clock level low or high
20
ns
Data Setup Time
t 4
5
ns
Data Hold Time
t 5
5
ns
FSYNC to SCLK active edge Setup Time
t 6
10
ns
SCLK to FSYNC Hold Time
t 7
0
ns
Minimum FSYNC High Time
t 8
35
ns
NOTES:
1.
Typicals represent average readings at +25°C and VDD = +5V.
2.
Guaranteed by design and not subject to production test.
3.
PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.
4.
See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics are
measured using VDD = +5V. Input logic should have a 1V/µsec minimum slew rate.


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