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TMP19A64C1DXBG Folha de dados(PDF) 9 Page - Toshiba Semiconductor |
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TMP19A64C1DXBG Folha de dados(HTML) 9 Page - Toshiba Semiconductor |
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9 / 460 page  TMP19A64C1D TMP19A64(rev1.1)2-3 2.2 Pin Names and Functions Table 2.2.1 shows the names and functions of input/output pins. Table 2.2.1 Pin Names and Functions (1 of 6) Pin name Number of pins Input or output Function P00-P07 D0-D7 AD0-AD7 8 Input/output Input/output Input/output Port 0: Input/output port that allows input/output to be set in units of bits Data (lower): Data buses 0 to 7 (separate bus mode) Address data (lower): Address data buses 0 to 7 (multiplexed bus mode) P10-P17 D8-D15 AD8-AD15 A8-A15 8 Input/output Input/output Input/output Output Port 1: Input/output port that allows input/output to be set in units of bits Data (upper): Data buses 8 to 15 (separate bus mode) Address data (upper): Address data buses 8 to 15 (multiplexed bus mode) Address: Address buses 8 to 15 (multiplexed bus mode) P20-P27 A16-A23 A0-A7 A16-A23 8 Input/output Output Output Output Port 2: Input/output port that allows input/output to be set in units of bits Address: Address buses 16 to 23 (separate bus mode) Address: Address buses 0 to 7 (multiplexed bus mode) Address: Address buses 16 to 23 (multiplexed bus mode) P30 RD 1 Output Output Port 30: Port used exclusively for output Read: Strobe signal for reading external memory P31 WR 1 Output Output Port 31: Port used exclusively for output Write: Strobe signal for writing data of D0 to D7 pins P32 HWR 1 Input/output Output Port 32: Input/output port (with pull-up) Write upper-pin data: Strobe signal for writing data of D8 to D15 pins P33 WAIT RDY 1 Input/output Input Input Port 33: Input/output port (with pull-up) Wait: Pin for requesting CPU to put a bus in a wait state Ready: Pin for notifying CPU that a bus is ready P34 BUSRQ 1 Input/output Input Port 34: Input/output port (with pull-up) Bus request: Signal requesting CPU to allow an external master to take the bus control authority P35 BUSAK 1 Input/output Output Port 35: Input/output port (with pull-up) Bus acknowledge: Signal notifying that CPU has released the bus control authority in response to BUSRQ P36 R/W 1 Input/output Output Port 36: Input/output port (with pull-up) Read/write: "1" shows a read cycle or a dummy cycle. "0" shows a write cycle. P37 ALE 1 Input/output Output Port 37: Input/output port Address latch enable (address latch is enabled only if access to external memory is taking place) P40 CS0 1 Input/output Output Port 40: Input/output port (with pull-up) Chip select 0: "0" is output if the address is in a designated address area. P41 CS1 1 Input/output Output Port 41: Input/output port (with pull-up) Chip select 1: "0" is output if the address is in a designated address area. P42 CS2 1 Input/output Output Port 42: Input/output port (with pull-up) Chip select 2: "0" is output if the address is in a designated address area. P43 CS3 1 Input/output Output Port 43: Input/output port (with pull-up) Chip select 3: "0" is output if the address is in a designated address area. P44 CS4 1 Input/output Output Port 44: Input/output port (with pull-up) Chip select 4: "0" is output if the address is in a designated address area. P45 CS5 1 Input/output Output Port 45: Input/output port (with pull-up) Chip select 5: "0" is output if the address is in a designated address area. P46 SCOUT 1 Input/output Output Port 46: Input/output port System clock output: Selectable between high- and low-speed clock outputs, as in the case of CPU P47 1 Input/output Port 47: Input/output port P50-P57 A0-A7 8 Input/output Output Port 5: Input/output port that allows input/output to be set in units of bits Address: Address buses 0 to 7 (separate bus mode) P60-P67 A8-A15 8 Input/output Output Port 6: Input/output port that allows input/output to be set in units of bits Address: Address buses 8 to 15 (separate bus mode) |
Nº de peça semelhante - TMP19A64C1DXBG |
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Descrição semelhante - TMP19A64C1DXBG |
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