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74LVQ573M Folha de dados(PDF) 1 Page - STMicroelectronics |
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74LVQ573M Folha de dados(HTML) 1 Page - STMicroelectronics |
1 / 10 page 74LVQ573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING ® February 1999 s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V s COMPATIBLE WITH TTL OUTPUTS s LOW POWER DISSIPATION: ICC =4 µA (MAX.) at TA =25 oC s LOW NOISE: VOLP = 0.5 V (TYP.) at VCC =3.3V s 75 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|=IOL = 24 mA (MIN) s PCI BUS LEVELS GUARANTEED AT 24mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for low power and low noise 3.3V applications. These 8 bit D-Type flip-flops are controlled by a latch enable input (LE) and an output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES : 74LVQ573M 74LVQ573T M (Micro Package) T (TSSOP Package) 1/10 |
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