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74LV259PW Folha de dados(PDF) 11 Page - NXP Semiconductors |
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74LV259PW Folha de dados(HTML) 11 Page - NXP Semiconductors |
11 / 19 page 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 11 of 19 NXP Semiconductors 74LV259 8-bit addressable latch Table 9. Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 12. Load circuit for switching times VCC VI VO 001aaa663 D.U.T. CL 50 pF RT RL 1 k Ω PULSE GENERATOR Table 10. Test data Supply voltage Input VCC VI tr, tf < 2.7 V VCC ≤ 2.5 ns 2.7 V to 3.6 V 2.7 V ≤ 2.5 ns |
Nº de peça semelhante - 74LV259PW |
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Descrição semelhante - 74LV259PW |
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