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AMU2481 Folha de dados(PDF) 6 Page - Micronas |
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AMU2481 Folha de dados(HTML) 6 Page - Micronas |
6 / 25 page AMU 2481 MICRONAS INTERMETALL 6 2.1.2. S–Bus Interface and S–Bus 2.1.2.1. Description of the S–Bus The S–bus was designed to connect the digital sound output of the DMA 2271 D2/MAC Decoder to audio– processing ICs such as the AMU 2481 Audio Mixer or the APU 2471 Audio Processor etc., and to connect these ICs with each other. The S–bus is an unidirec- tional, digital bus which transmits the sound information in one direction only, so that it is not necessary to solve priority problems on the bus. The S–bus consists of the three lines S–Clock, S–Ident and S–Data. The DMA 2271 generates the signals S– Clock and S–Ident, which control the data transfer to and between the various processors which follow the DMA 2271. For this, the S–Clock and S–Ident inputs of all processors in the system are connected to the S–Clock and S–Ident outputs of the DMA 2271. S–data output of the DMA 2271 is connected to the S–Data input of the next following AMU, the AMU’s S–Data output is con- nected to the APU’s S–Data input and so on. The sound information is transmitted in frames of 64 bits, divided into four successive 16–bit samples. Each sam- ple represents one sound channel. The timing of a com- plete transmission of four samples is shown in Fig. 2–1, the times are specified in “Recommended Operating Conditions”. The transmission starts with the LSB of the first sample. The S–Clock signal is used to write the data into the receiver’s input register. The S–Ident signal marks the end of one frame of 64 bits and is used as latch pulse for the input register. The repetition rate of the S–Ident pulses is identical to the sampling rate of the D2–MAC sound signal; thus it is possible to transfer four sound channels simultaneously. 2.1.2.2. The S–Bus Interface The S–bus interface of the AMU 2481 mainly consists of an input and an output register, each 64–bit wide. The timing to write or read bit by bit is supplied by the S– Clock signal. In the case of an S–Ident pulse, the con- tents of the input register are transferred to the data RAM (see section 2.2.1.) and the contents of the output register are written to the S–Data output. The S–Ident is also used as the sampling rate reference for the DSP software in the case of digital source mode. In this mode the IOSYNC generated by the decimation filters is locked to the S–Ident. This allows a mixed mode: S–Data and PDM Data can be processed simul- taneously. In this case, however, there must be the same audio sample rate of PDM data and S–bus data (see 2.3.). If this is not the case, the S–Ident line has to be dis- abled. By means of coefficient k33 (see section 3.13.) the AMU 2481 can be switched to an S–bus slave mode (bit 4 = 0) or to an S–bus master mode (bit 4 = 1). The slave mode is required in an application as shown in Fig. 1–2 where the DMA 2271 D2–MAC Decoder acts as master on the S–bus, i.e. the DMA 2271 supplies the S–Clock and S– Ident signals as well as the S–Data input signal. To enable parallel cascading of AMUs without external switches, (e.g. NICAM to SCART and D2MAC to TV) in the 44–PLCC package, the SBUS signals S–Ident and S–Clock, (and the Main Clock, see section 2.3.) can be passed through the AMU 2481. The corresponding open–drain outputs can be switched to high impedance, which is the default status after power–on reset. To switch them on or off (high imp.), use the same bit that controls the SBUS data output: k33 bit3 = 0 outputs = active = 1 outputs = high impedance 2.1.3. IM Bus Interface and IM Bus 2.1.3.1. Description of the IM Bus The INTERMETALL Bus (IM Bus for short) was de- signed to control the DIGIT 2000 ICs by the CCU Central Control Unit. Via this bus the CCU can write data to the ICs or read data from them. This means the CCU acts as a master whereas all controlled ICs are slaves.The IM bus consists of three lines for the signals Ident (ID), Clock (CL) and Data (D). The clock frequency range is 50 Hz to 170 kHz. Ident and clock are unidirectional from the CCU to the slave ICs, Data is bidirectional. Bidirec- tionality is achieved by using open–drain outputs with On–resistances of 150 Ohm maximum. The 2.5 kOhm pull–up resistor common to all outputs is incorporated in the CCU.The timing of a complete IM bus transaction is shown in Fig. 2–2 and in the “Recommended Operating Conditions”. In the non–operative state the signals of all three bus lines are High. To start a transaction the CCU sets the ID signal to Low level, indicating an address transmission, then sets the CL signal to Low level and switches the first bit on the Data line.Then eight address bits are transmitted, beginning with the LSB. Data take- over in the slave ICs occurs at the positive edge of the clock signal. At the end of the address byte the ID signal goes High, initiating the address comparison in the slave circuits. In the addressed slave the IM bus interface switches over to Data read or write, because these func- tions are correlated to the address. Also controlled by the address the CCU now transmits eight or sixteen clock pulses, and accordingly one or two Bytes of data are written into the addressed IC or read out from it, beginning with the LSB. The completion of the bus transaction is signalled by a short Low state pulse of the ID signal. This initiates the storing of the transferred data. It is permissible to interrupt a bus transaction for up to 10 ms. |
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