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M74HC4518F1R Folha de dados(PDF) 1 Page - STMicroelectronics |
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1 / 13 page M54/M74HC4518 M54/M74HC4520 March 1993 HC4520 DUAL 4 BIT BINARY COUNTER HC4518 DUAL DECADE COUNTER B1R (Plastic Package) ORDER CODES : M54HCXXXXF1R M74HCXXXXM1R M74HCXXXXB1R M74HCXXXXC1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal Connection DESCRIPTION . HIGH SPEED fMAX = 55 MHz (TYP.) at VCC =5 V . LOW POWER DISSIPATION ICC =4 µA (MAX.) AT TA =25 °C . HIGH NOISE IMMUNITY VNIH =VNIL =28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE |IOH|= IOL = 4 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH =tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 4520B/4518B The M54/74HC4518/4520 are high speed CMOS DUAL 4 BIT BINARY COUNTERS fabricated in sili- con gate C 2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. They consists of two identical internally syn- chronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable Clock and ENABLE inputs for incrementing on either the posi- tive-going or negative-going transition. For single-unit operation the ENABLE input is main- tained ”high” and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their clear lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the clock input of the latter is held permanently low. All inputs are equipped with protection circuits against static discharge and transient excess volt- age. 1/13 |
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