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TL16C451FNRG4 Folha de dados(PDF) 5 Page - Texas Instruments |
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TL16C451FNRG4 Folha de dados(HTML) 5 Page - Texas Instruments |
5 / 24 page TL16C451, TL16C452 ASYNCHRONOUS COMMUNICATIONS ELEMENTS SLLS053C – MAY 1989 – REVISED AUGUST 1999 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME† NO. I/O DESCRIPTION A0 A1 A2 35 34 33 I Register select. A0, A1, and A2 are used during read and write operations to select the register to read from or write to. Refer to Table 1 for register addresses, also refer to the chip select signals (CS0, CS1, CS2). ACK 68 I Printer acknowledge. ACK goes low to indicate that a successful data transfer has taken place. It generates a printer port interrupt during its positive transition. AFD 56 I/O Printer autofeed. AFD is an open-drain line that provides the printer with a low signal when continuous-form paper is to be autofed to the printer. An internal pullup is provided. BDO 44 O Bus buffer output. BDO is active (high) when the CPU is reading data. When active, this output can disable an external transceiver. BUSY 66 I Printer busy. BUSY is an input line from the printer that goes high when the printer is not ready to accept data. CLK 4 I/O External clock. CLK connects the ACE to the main timing reference. CS0 CS1 [VCC] CS2 32 3 38 I Chip selects. Each chip select enables read and write operations to its respective channel. CS0 and CS1 select serial channels 0 and 1, respectively, and CS2 selects the parallel port. CTS0 CTS1 [GND] 28 13 I Clear to send. CTSx is an active-low modem status signal. Its state can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTSx changes state, an interrupt is generated. DB0 – DB7 14 – 21 I/O Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the TL16C451/TL16C452 and the CPU. DB0 is the least significant bit (LSB). DSR0 DSR1 [GND] 31 5 I Data set ready. DSRx is an active-low modem status signal. Its state can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DSRx changes state, an interrupt is generated. DTR0 DTR1 [NC] 25 11 O Data terminal ready. DTRx, when active (low), informs a modem or data set that the ACE is ready to establish communication. DTRx is placed in the active state by setting the DTR bit of the modem control register. DTRx is placed in the inactive state either as a result of a reset or during loop mode operation or clearing bit 0 (DTR) of the modem control register. ERROR 63 I Printer error. ERROR is an input line from the printer. The printer reports an error by holding this line low during the error condition. INIT 57 I/O Printer initialize. INIT is an open-drain line that provides the printer with a signal that allows the printer initialization routine to be started. An internal pullup is provided. INT0 INT1 [NC] 45 60 O Interrupt. INTx is an active-high 3-state output that is enabled by bit 3 of the MCR. When active, INTx informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data is available, the transmitter holding register is empty, and an enabled modem status interrupt. The INTx output is reset (low) either when the interrupt is serviced or as a result of a reset. INT2 59 O Printer port interrupt. INT2 is an active-high 3-state output generated by the positive transition of ACK. It is enabled by bit 4 of the write control register. IOR 37 I Data read strobe. When IOR input is active (low) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. IOW 36 I Data write strobe. When IOW input is active (low) while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. LPTOE 1 I Parallel data output enable. When low, LPTOE enables the write data register to the PD0 – PD7 lines. A high puts the PD0 – PD7 lines in the high-impedance state allowing them to be used as inputs. LPTOE is usually tied low for printer operation. † Names shown in brackets are for the TL16C451. |
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