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SN74ABT16821DLRG4 Folha de dados(PDF) 6 Page - Texas Instruments |
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SN74ABT16821DLRG4 Folha de dados(HTML) 6 Page - Texas Instruments |
6 / 12 page SN54ABT16821, SN74ABT16821 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS216B – JUNE 1992 – REVISED JANUARY 1997 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION 1.5 V th tsu From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 7 V Open GND 500 Ω 500 Ω Data Input Timing Input 1.5 V 3 V 0 V 1.5 V 1.5 V 3 V 0 V 3 V 0 V 1.5 V 1.5 V tw Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL tPHL tPLH VOH VOH VOL VOL 1.5 V 1.5 V 3 V 0 V 1.5 V 1.5 V Input 1.5 V Output Control Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ 1.5 V 1.5 V 3.5 V 0 V 1.5 V VOL + 0.3 V 1.5 V VOH – 0.3 V [ 0 V 3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Output Output tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7 V Open TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms |
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