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ST93CS47M6013TR Folha de dados(PDF) 7 Page - STMicroelectronics

Nome de Peças ST93CS47M6013TR
Descrição Electrónicos  1K 64 x 16 SERIAL MICROWIRE EEPROM
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

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Output data changes are triggered by the Low to
High transition of the Clock (C). The ST93CS46/47
will automatically increment the address and will
clock out the next word as long as the Chip Select
input (S) is held High. In this case the dummy ’0’ bit
is NOT output between words and a continuous
stream of data can be read.
Write Enable and Write Disable
The Write Enable instruction (WEN) authorizes the
following Write instructions to be executed, the
Write Disable instruction (WDS) disables the exe-
cution of the following Erase/Write instructions.
When power is first applied, the ST93CS46/47
enters the Disable mode. When the Write Enable
instruction (WEN) is executed, Write instructions
remain enabled until a Write Disable instruction
(WDS) is executed or if the Power-on reset circuit
becomes active due to a reduced VCC. To protect
the memory contents from accidental corruption, it
is advisable to issue the WDS instruction after
every write cycle.
The READ instruction is not affected by the WEN
or WDS instructions.
Write
The Write instruction (WRITE) is followed by the
address and the word to be written. The Write
Enable signal (W) must be held high during the
WRITE instruction. Data input D is sampled on the
Low to High transition of the clock. After the last
data bit has been sampled, Chip Select (S) must
be brought Low before the next rising edge of the
clock (C), in order to start the self-timed program-
ming cycle, providing that the address is NOT in the
protected area. If the ST93CS46/47 is still per-
forming the programming cycle, the Busy signal (Q
= 0) will be returned if the Chip Select input (S) is
driven high, and the ST93CS46/47 will ignore any
data on the bus. When the write cycle is completed,
the Ready signal (Q = 1) will indicate (if S is driven
high) that the ST93CS46/47 is ready to receive a
new instruction.
Page Write
A Page Write instruction (PAWRITE) contains the
first address to be written followed by up to 4 data
words. The Write Enable signal (W) must be held
High duringthe Write instruction. Input address and
data are read on the Low to High transition of the
clock. After the receipt of each data word, bits
A1-A0 of the internal address register are incre-
mented, the high order bits A5-A2 remaining un-
changed. Users must take care by software to
ensure that the last word address has the same
four upper order address bits as the initial address
transmitted to avoid address roll-over.
After the LSB of the last data word, Chip Select (S)
must be brought Low before the next rising edge of
the Clock (C). The falling edge of Chip Select (S)
initiates the internal, self-timed write cycle. The
Page Write operation will not be performed if any
of the 4 words is addressing the protected area. If
the ST93CS46/47 is still performing the program-
ming cycle, the Busy signal (Q = 0) will be returned
if the Chip Select input (S) is driven high, and the
ST93CS46/47 will ignore any data on the bus.
When the write cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the ST93CS46/47 is ready to receive a new instruc-
tion.
Write All
The Write All instruction (WRALL) is valid only after
the Protect Register has been cleared by executing
a PRCLEAR (Protect Register Clear) instruction.
The Write All instruction simultaneously writes the
whole memory with the same data word included
in the instruction. The Write Enable signal (W) must
be held High before and during the Write instruc-
tion. Input address and data are read on the Low
to High transition of the clock. If the ST93CS46/47
is still performing the programming cycle, the Busy
signal (Q = 0) will be returned if the Chip Select
input (S) is driven high, and the ST93CS46/47 will
ignore any data on the bus. When the write cycle
is completed, the Ready signal (Q = 1) will indicate
(if S is driven high) that the ST93CS46/47 is ready
to receive a new instruction.
MEMORY WRITE PROTECTION AND PROTECT
REGISTER
The ST93CS46/47 offers a Protect Register con-
taining the bottom address of the memory area
which has to be protected against write instruc-
tions. In addition to this Protect Register, two flag
bits are used to indicate the Protect Register status:
the Protect Flag enabling/disabling the protection
of theProtect Register and the OTP bit which, when
set, disables access to the Protect Register and
thus prevents any further modifications of this Pro-
tect Register value. The content of the Protect
Register is defined when using the PRWRITE in-
struction, it may be read when using the PRREAD
instruction. A specific instruction PREN (Protect
Register Enable) allows the user to execute the
protect instructions PRCLEAR, PRWRITE and
PRDS; this PREN instruction being used together
with the signals applied on the input pins PRE
(Protect Register Enable pin) and W (Write En-
able).
7/16
ST93CS46, ST93CS47


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