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M74HC40103 Folha de dados(PDF) 2 Page - STMicroelectronics |
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M74HC40103 Folha de dados(HTML) 2 Page - STMicroelectronics |
2 / 16 page M74HC40103 2/16 (25510) regardless of the state of any other input. The precedence relationship between control input is indicated in the truth table. If all control inputs are high at the time of zero count, the counters will jump to the maximum count giving a INPUT AND OUTPUT EQUIVALENT CIRCUIT counting sequence of 256 clock pulses long. The HC40103 may be cascaded using the CI/CE input and the CO/ZD output, in either a synchronous or ripple mode. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN DESCRIPTION TRUTH TABLE X : Don’t Care Maximum Count is "255" PIN No SYMBOL NAME AND FUNCTION 1 CLOCK Clock Input (LOW to HIGH edge triggered) 2 CLEAR Asynchronous Master Reset Input (Active Low) 3 CI/CE Terminal Enable Input 4, 5, 6, 7, 10, 11, 12, 13 J0 to J9 Jam Inputs 9APE Asynchronous Preset Enable Inputs(Active Low) 14 CO/ZD Terminal Count Output (Active Low) 15 SPE Synchronous Preset Enable Input (Active Low) 8 GND Ground (0V) 16 Vcc Positive Supply Voltage CONTROL INPUTS MODE FUNCTIONAL DESCRIPTION CLEAR APE SPE CI/CE H H H H COUNT INHIBIT EVEN IF CLOCK IS GIVEN, NO COUNT IS MADE H H H L REGULAR COUNT DOWN COUNT AT RISING EDGE OF CLOCK HH L X SYNCHRONOUS PRESET DATA OF PI TERMINAL IS PRESET AT RISING EDGE OF CLOCK HL XX ASYNCHRONOUS PRESET DATA OF PI TERMINAL IS ASYNCHRONOUSLY PRESET TO CLOCK L X X X CLEAR COUNTER IS SET TO MAXIMUM COUNT |
Nº de peça semelhante - M74HC40103 |
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Descrição semelhante - M74HC40103 |
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