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LFXP28E6CM132I Folha de dados(PDF) 10 Page - Lattice Semiconductor

Nome de Peças LFXP28E6CM132I
Descrição Electrónicos  LatticeXP2 Family Data Sheet
Download  92 Pages
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Fabricante Electrônico  LATTICE [Lattice Semiconductor]
Página de início  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFXP28E6CM132I Folha de dados(HTML) 10 Page - Lattice Semiconductor

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2-7
Architecture
Lattice Semiconductor
LatticeXP2 Family Data Sheet
Figure 2-4. General Purpose PLL (GPLL) Diagram
Table 2-4 provides a description of the signals in the GPLL blocks.
Table 2-4. GPLL Block Signal Descriptions
Clock Dividers
LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These are
intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or
÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock
based on the release of its reset signal. The clock dividers can be fed from the CLKOP output from the GPLLs or
from the Edge Clocks (ECLK). The clock divider outputs serve as primary clock sources and feed into the clock dis-
tribution network. The Reset (RST) control signal resets the input and forces all outputs to low. The RELEASE sig-
nal releases outputs to the input clock. For further information on clock dividers, please see TN1126, sysCLOCK
PLL Design and Usage Guide. Figure 2-5 shows the clock divider connections.
Signal
I/O
Description
CLKI
I
Clock input from external pin or routing
CLKFB
I
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
RST
I
“1” to reset PLL counters, VCO, charge pumps and M-dividers
RSTK
I
“1” to reset K-divider
DPHASE [3:0]
I
DPA Phase Adjust input
DDDUTY [3:0]
I
DPA Duty Cycle Select input
WRDEL
I
DPA Fine Delay Adjust input
CLKOS
O
PLL output clock to clock tree (phase shifted/duty cycle changed)
CLKOP
O
PLL output clock to clock tree (no phase shift)
CLKOK
O
PLL output to clock tree through secondary clock divider
CLKOK2
O
PLL output to clock tree (CLKOP divided by 3)
LOCK
O
“1” indicates PLL LOCK to CLKI
CLKFB
Divider
RST
CLKFB
CLKI
LOCK
CLKOP
CLKOS
RSTK
DPHASE
Internal Feedback
DDUTY
WRDEL
CLKOK2
CLKOK
CLKI
Divider
PFD
VCO/
LOOP FILTER
CLKOP
Divider
Phase/
Duty Cycle/
Duty Trim
Duty Trim
CLKOK
Divider
Lock
Detect
3


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