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LC4128ZC-75TN100I Folha de dados(PDF) 11 Page - Lattice Semiconductor |
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LC4128ZC-75TN100I Folha de dados(HTML) 11 Page - Lattice Semiconductor |
11 / 99 page Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 11 Table 10. ORP Combinations for I/O Blocks with 12 I/Os ORP Bypass and Fast Output Multiplexers The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also allows the register output to bypass the ORP to achieve faster tCO. Output Enable Routing Multiplexers The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell. I/O Cell The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus maintenance circuitry. Figure 8 details the I/O cell. Figure 8. I/O Cell Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde- pendent of the VCCO supplied to its I/O bank. The I/O standards supported are: I/O Cell Available Macrocells I/O 0 M0, M1, M2, M3, M4, M5, M6, M7 I/O 1 M1, M2, M3, M4, M5, M6, M7, M8 I/O 2 M2, M3, M4, M5, M6, M7, M8, M9 I/O 3 M4, M5, M6, M7, M8, M9, M10, M11 I/O 4 M5, M6, M7, M8, M9, M10, M11, M12 I/O 5 M6, M7, M8, M9, M10, M11, M12, M13 I/O 6 M8, M9, M10, M11, M12, M13, M14, M15 I/O 7 M9, M10, M11, M12, M13, M14, M15, M0 I/O 8 M10, M11, M12, M13, M14, M15, M0, M1 I/O 9 M12, M13, M14, M15, M0, M1, M2, M3 I/O 10 M13, M14, M15, M0, M1, M2, M3, M4 I/O 11 M14, M15, M0, M1, M2, M3, M4, M5 GOE 0 From ORP *Global fuses From ORP To Macrocell To GRP GOE 1 GOE 2 GOE 3 VCC VCCO VCCO ** * |
Nº de peça semelhante - LC4128ZC-75TN100I |
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Descrição semelhante - LC4128ZC-75TN100I |
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