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SN74SSQE32882ZCJR Folha de dados(PDF) 1 Page - Texas Instruments

Nome de Peças SN74SSQE32882ZCJR
Descrição Electrónicos  28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

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FEATURES
APPLICATIONS
DESCRIPTION/ORDERING INFORMATION
SN74SSQE32882
www.ti.com .................................................................................................................................................................................................. SCAS857 – MARCH 2008
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST
ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER
First, when the QCSEN input pin is open or pulled
high, the component has two chip select inputs,
2
• 1-to-2 Register Outputs and 1-to-4 Clock Pair
DCS0 and DCS1, and two copies of each chip select
Outputs Support Stacked DDR3 DIMMs
output, QACS0, QACS1, QBCS0 and QBCS1. This
• Chip Select Inputs Prevent Data Outputs from
mode is the QuadCS disabled mode. Alternatively,
Changing State and Minimize System Power
when the QCSEN input pin is pulled low, the
Consumption
component has four chip select inputs DCS[3:0], and
four chip select outputs, QCS[3:0]. This mode is the
• 1.5-V Phase Lock Loop Clock Driver Buffers
QuadCS enabled mode.
One Differential Clock Pair (CK and CK) and
Distributes to Four Differential Outputs
When QCSEN is high or floating, the device also
supports an operating mode that allows a single
• 1.5-V CMOS Inputs
device to be mounted on the back side of a DIMM
• Checks Parity on Command and Address
array. This device can then be configured to keep the
(CS-gated) Data Inputs
input bus termination (IBT) feature enabled for all
• Supports LVCMOS Switching Levels on
input
signals
independent
of
MIRROR.
The
SN74SSQE32882. operates from a differential clock
RESET Input
(CK and CK). Data are registered at the crossing of
• RESET Input:
CK going high and CK going low. This data can either
Disables Differential Input Receivers
be re-driven to the outputs or used to access internal
Resets All Registers
control registers. Details are covered in the Function
Tables (each flip-flop) with QCSEN = low.
Forces All Outputs into Pre-defined States
Input bus data integrity is protected by a parity
• Optimal Pinout for DDR3 DIMM PCB Layout
function. All address and command input signals are
• Supports Four Chip Selects
summed; the last bit of the sum is then compared to
• Single Register Backside Mount Support
the parity signal delivered by the system at the
PAR_IN input one clock cycle later. If these two
values do not match, the device pulls the open drain
output ERROUT low. The control signals (DCKE0,
• DDR3-Registered DIMMs
DCKE1, DODT0, DODT1, and DCS[n:0]) are not part
• Quad-Rank RDIMM
of this computation.
The
SN74SSQE32882
implements
different
power-saving mechanisms to reduce thermal power
This JEDEC standard, 28-bit 1:2 or 26-bit 1:2 and
dissipation and to support system power-down states.
4-bit 1:1 registering clock driver with parity is
Power consumption is further reduced by disabling
designed for operation on DDR3-registered DIMMs
unused outputs.
with VDD of 1.5 V.
The package design is optimal for high-density
All inputs are 1.5-V, CMOS-compatible. All outputs
DIMMs. By aligning input and output positions
are 1.5-V CMOS drivers optimized to drive DRAM
towards DIMM finger-signal ordering and SDRAM
signals on terminated traces in DDR3 RDIMM
ballout, the device de-scrambles the DIMM traces
applications. Clock outputs Yn and Yn and control net
and
allows
low
crosstalk
designs
with
low
outputs DxCKEn, DxCSn, and DxODTn can each be
interconnect latency. Edge-controlled outputs reduce
driven with a different strength and skew to optimize
ringing and improve signal eye opening at the
signal integrity, compensate for different loading, and
SDRAM inputs.
balance signal travel speed.
Throughout this document, DCS[n:0] indicates all of
The SN74SSQE32882 has two basic modes of
the chip select inputs, where n = 1 for QuadCS
operation associated with the Quad Chip Select
disabled, and n = 3 for QuadCS enabled. QxCS[n:0]
Enable (QCSEN) input.
indicates all of the chip select outputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated


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