1

Data sheet acquired from Harris Semiconductor

SCHS185

Features

• Two BCD Decade or Bi-Quinary Counters

• One Package Can Be Configured to Divide-by-2, 4,

5,10, 20, 25, 50 or 100

• Two Master Reset Inputs to Clear Each Decade

Counter Individually

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

Pinout

CD74HC390, CD74HCT390

TOP VIEW

Description

The Harris CD74HC390 and CD574HCT390 dual 4-bit

decade ripple counters are high-speed silicon-gate CMOS

devices and are pin compatible with low-power Schottky TTL

(LSTTL). These devices are divided into four separately

clocked sections. The counters have two divide-by-2 sec-

tions and two divide-by-5 sections. These sections are nor-

mally used in a BCD decade or bi-quinary configuration,

since they share a common master reset (nMR). If the two

master reset inputs (1MR and 2MR) are used to simulta-

neously clear all 8 bits of the counter, a number of counting

configurations are possible within one package. The sepa-

rate clock inputs (nCP0 and nCP1) of each section allow rip-

ple counter or frequency division applications of divide-by-2,

4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the

High-to-Low transition of the input pulses (nCP0 and nCP1).

For BCD decade operation, the nQ0 output is connected to

the nCP1 input of the divide-by-5 section. For bi-quinary

decade operation, the nO3 output is connected to the nCP0

The master reset inputs (1MR and 2MR) are active-High

asynchronous inputs to each decade counter which oper-

ates on the portion of the counter identified by the “1” and “2”

prefixes in the pin configuration. A High level on the nMR

input overrides the clock and sets the four outputs Low.

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

1CP0

1MR

1CP1

GND

2MR

2Q0

2CP1

2CP0

Ordering Information

PART NUMBER

PACKAGE

PKG.

NO.

CD74HC390E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT390E

-55 to 125

16 Ld PDIP

E16.3

CD74HC390M

-55 to 125

16 Ld SOIC

M16.15

CD74HCT390M

-55 to 125

16 Ld SOIC

M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer for this part number is available which meets all electrical

specifications. Please contact your local sales office or Harris

customer service for ordering information.

September 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

File Number

1838.2

CD74HC390,

CD74HCT390

High Speed CMOS Logic

Dual Decade Ripple Counter

[ /Title

(CD74

HC390

,

CD74

HCT39

0)

/Sub-

ject

(High

Speed

CMOS