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SN74ABT3614PCB Folha de dados(PDF) 7 Page - Texas Instruments

Nome de Peças SN74ABT3614PCB
Descrição Electrónicos  64 횞 36 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
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SN74ABT3614PCB Folha de dados(HTML) 7 Page - Texas Instruments

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SN74ABT3614
64
× 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
reset (continued)
Table 1. Flag Programming
FS1
FS0
RST
AF AND AE FLAG
OFFSET REGISTER (X)
H
H
16
H
L
12
L
H
8
L
L
4
FIFO write/read operation
The state of the port-A data (A0 – A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0 – A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0 – A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the
A0 – A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low,
and FFA is high. Data is read from FIFO2 to the A0 – A35 outputs by a low-to-high transition of CLKA when CSA
is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2).
Table 2. Port-A Enable Function Table
CSA
W/RA
ENA
MBA
CLKA
A0 – A35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
In high-impedance state
FIFO1 write
L
H
H
H
In high-impedance state
Mail1 write
L
L
L
L
X
Active, FIFO2 output register
None
L
L
H
L
Active, FIFO2 output register
FIFO2 read
L
L
L
H
X
Active, mail2 register
None
L
L
H
H
Active, mail2 register
Mail2 read (set MBF2 high)
The state of the port-B data (B0 – B35) outputs is controlled by the port-B chip select (CSB) and the port-B
write/read select (W/RB). The B0 – B35 outputs are in the high-impedance state when either CSB or W/RB is
high. The B0 – B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIFO2 from the
B0 – B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, FFB is high,
and either SIZ0 or SIZ1 is low. Data is read from FIFO1 to the B0 – B35 outputs by a low-to-high transition of
CLKB when CSB is low, W/RB is low, ENB is high, EFB is high, and either SIZ0 or SIZ1 is low (see Table 3).
The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
can change states during the setup- and hold-time window of the cycle.


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