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SN74ACT3622PQ Folha de dados(PDF) 10 Page - Texas Instruments

Nome de Peças SN74ACT3622PQ
Descrição Electrónicos  256 횞 36 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SN74ACT3622PQ Folha de dados(HTML) 10 Page - Texas Instruments

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SN74ACT3622
256
× 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247D – AUGUST 1993 – REVISED APRIL 1998
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
input-ready flags (IRA, IRB)
The IR flag of a FIFO is synchronized to the port clock that writes data to its array. When the IR flag is high, a
memory location is free in the SRAM to receive new data. No memory locations are free when the IR flag is low
and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. From the time a word is read from a FIFO,
its previous memory location is ready to be written in a minimum of two cycles of the IR flag synchronizing clock;
therefore, an IR flag is low if less than two cycles of the IR flag synchronizing clock have elapsed since the next
memory write location has been read. The second low-to-high transition on the IR flag synchronizing clock after
the read sets the IR flag high.
A low-to-high transition on an IR flag synchronizing clock begins the first synchronization cycle of a read if the
clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figures 9 and 10).
almost-empty flags (AEA, AEB)
The AE flag of a FIFO is synchronized to the port clock that reads data from its array. The AE state is defined
by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values
during a FIFO reset or programmed from port A (see
almost-empty flag and almost-full flag offset programming).
An AE flag is low when its FIFO contains X or fewer words and is high when its FIFO contains (X + 1) or more
words. A data word present in the FIFO output register has been read from memory.
Two low-to-high transitions of the AE flag synchronizing clock are required after a FIFO write for its AE flag to
reflect the new level of fill; therefore, the AE flag of a FIFO containing (X + 1) or more words remains low if two
cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X + 1) level. An
AE flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO write that fills
memory to the (X + 1) level. A low-to-high transition of an AE flag synchronizing clock begins the first
synchronization cycle if it occurs at time tsk2, or greater, after the write that fills the FIFO to (X + 1) words.
Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 11 and
12).
almost-full flags (AFA, AFB)
The AF flag of a FIFO is synchronized to the port clock that writes data to its array. The AF state is defined by
the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during
a FIFO reset or programmed from port A (see
almost-empty flag and almost-full flag offset programming). An
AF flag is low when the number of words in its FIFO is greater than or equal to (256 – Y). An AF flag is high when
the number of words in its FIFO is less than or equal to [256 – (Y + 1)]. A data word present in the FIFO output
register has been read from memory.
Two low-to-high transitions of the AF flag synchronizing clock are required after a FIFO read for its AF flag to
reflect the new level of fill; therefore, the AF flag of a FIFO containing [256 – (Y + 1)] or fewer words remains
low if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words
in memory to [256 – (Y + 1)]. An AF flag is set high by the second low-to-high transition of its synchronizing clock
after the FIFO read that reduces the number of words in memory to [256 – (Y + 1)]. A low-to-high transition of
an AF flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the
read that reduces the number of words in memory to [256 – (Y + 1)]. Otherwise, the subsequent synchronizing
clock cycle can be the first synchronization cycle (see Figures 13 and 14).


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