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TL16C754BFN Folha de dados(PDF) 3 Page - Texas Instruments |
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TL16C754BFN Folha de dados(HTML) 3 Page - Texas Instruments |
3 / 37 page TL16C754B QUAD UART WITH 64-BYTE FIFO SLLS397 – NOVEMBER 1999 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION NAME PN FN A0 30 34 I Address bit 0 select. Internal registers address selection. Refer to Table 7 for Register Address Map. A1 29 33 I Address bit 1 select. Internal registers address selection. Refer to Table 7 for Register Address Map A2 28 32 I Address bit 2 select. Internal registers address selection. Refer to Table 7 for Register Address Map CDA, CDB CDC, CDD 79, 23 39, 63 9, 27 43, 61 I Carrier detect (active low). These inputs are associated with individual UART channels A through D. A low on these pins indicates that a carrier has been detected by the modem for that channel. CLKSEL 26 30 I Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset, a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL selects the divide-by-4 prescaler. The value of CLKSEL is latched into MCR[7] at the trailing edge of RESET. A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on CLKSEL will latch a 1 into MCR[7]. MCR[7] can be changed after RESET to alter the prescaler value. CSA, CSB CSC, CSD 9, 13, 49, 53 16, 20, 50, 54 I Chip select A, B, C, and D (active low). These pins enable data transfers between the user CPU and the TL16C754B for the channel(s) addressed. Individual UART sections (A, B, C, D) are addressed by providing a low on the respective CSA through CSD pin. CTSA, CTSB CTSC, CTSD 4, 18 44, 58 11, 25 45, 59 I Clear to send (active low). These inputs are associated with individual UART channels A through D. A low on the CTS pins indicates the modem or data set is ready to accept transmit data from the 754A. Status can be checked by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation. D0–D2 D3–D7 68–70, 71–75 66–68, 1–5 I/O Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. DSRA, DSRB DSRC, DSRD 3, 19 43, 59 10, 26 44, 60 I Data set ready (active low). These inputs are associated with individual UART channels A through D. A low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART. DTRA, DTRB DTRC, DTRD 5, 17 45, 57 12, 24 46, 58 O Data terminal ready (active low). These outputs are associated with individual UART channels A through D. A low on these pins indicates that the 754A is powered on and ready. These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset. GND 16, 36, 56, 76 6, 23, 40, 57 Pwr Signal and power ground INTA, INTB INTC, INTD 8, 14, 48, 54 15, 21, 49, 55 O Interrupt A, B, C, and D (active high). These pins provide individual channel interrupts, INTA-D. INTA–D are enabled when MCR bit 3 is set to a 1, interrupts are enabled in the interrupt enable register (IER) and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. INTA–D are in the high-impedance state after reset. INTSEL 67 65 I Interrupt select (active high with internal pulldown). INTSEL can be used in conjunction with MCR bit 3 to enable or disable the 3-state interrupts INTA-D or override MCR bit 3 and force continuous interrupts. Interrupt outputs are enabled continuously by making this pin a 1. Driving this pin low allows MCR bit 3 to control the 3-state interrupt output. In this mode, MCR bit 3 is set to a 1 to enable the 3-state outputs. IOR 51 52 I Read input (active low strobe). A valid low level on IOR will load the contents of an internal register defined by address bits A0–A2 onto the TL16C754B data bus (D0–D7) for access by an external CPU. IOW 11 18 I Write input (active low strobe). A valid low level on IOW will transfer the contents of the data bus (D0–D7) from the external CPU to an internal register that is defined by address bits A0–A2. |
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