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TL16PNP550AFN Folha de dados(PDF) 6 Page - Texas Instruments |
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TL16PNP550AFN Folha de dados(HTML) 6 Page - Texas Instruments |
6 / 40 page TL16PNP550A ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL SLLS190B – MARCH 1995 – REVISED MARCH 1996 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL NAME NO. FN I/O DESCRIPTION A0 – A6 A7 – A11 32 – 38 40 – 44 I 12-bit ISA address terminals. All 12 bits are used during PnP autoconfiguration sequence. After autoconfiguration, bits A0 – A2 select the ACE registers and bits A3 – A9 are used in the address decoding to generate chip select for the device. ACONFIG0, ACONFIG1 67, 68 I Address configure. In PnP bypass mode, both ACONFIG0 and ACONFIG1 configure the COM port base address. AEN 46 I Address enable. AEN disables the ACE and PnP controller during DMA. CS 54 O Chip select. CS is a 3-state output. It controls the activity of the EEPROM. A 100 µA pulldown circuit is connected to this terminal. CS 30 O Chip select. CS is the I/O chip select for the logical device. CTS 60 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register (MSR). Bit 0 ( ∆CTS) of the modem status register indicates that this signal has changed states since the last read from the MSR. When the modem status interrupt is enabled when CTS changes states and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter. D0 – D3 D4 – D7 10 – 13 15 – 18 I/O Data bus. D0 – D7 are eight data lines with 3-state outputs that provide a bidirectional path for data, control, and status information between the ACE and the CPU. The output drive sinks 24 mA at 0.4 V and sources 12 mA at 2.4 V. DCD 59 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the MSR. Bit 3 ( ∆DCD) of the MSR indicates that this signal has changed levels since the last read from the MSR. When the modem status interrupt is enabled when DCD changes states, an interrupt is generated. DSR 62 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the MSR. Bit 1 ( ∆DSR) of the MSR indicates this signal has changed states since the last read from the MSR. If the modem status interrupt is enabled when the DSR changes states, an interrupt is generated. DTR 50 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR is placed in its active level by setting the DTR bit of the MCR. DTR is placed in its inactive level either as a result of a master reset, during loop mode operation, or clearing the DTR bit. EEPROM 58 I/O EEPROM access. EEPROM is a 3-state bidirectional signal. When it is pulled low, either the TL16PNP550A or controller is accessing the EEPROM. A 100 µA pullup circuit is connected to this terminal. EXINTR 47 I External interrupt. During UARTBYPASS mode, the external logical device interrupt (EXINTR) is mapped to the configured IRQs. GND 14, 31, 48, 65 Ground (0 V). These four GND terminals must be tied to ground for proper operation. ICONFIG0 – ICONFIG3 1–4 I IRQ configure. In PnP bypass mode, ICONFIG0 , ICONFIG2, and ICONFIG3 configure the required IRQ. IOR 8 I Read input. When IOR is active while the ACE is selected, the CPU is allowed to read from the ACE. IOW 9 I Write input. When IOW is active while the ACE is selected, the CPU is allowed to write to the ACE. IRQ3 – IRQ4 IRQ5 – IRQ7 IRQ9 – IRQ12 IRQ15 20 – 21 23 – 25 26 – 29 19 O 3-state interrupt requests. When active (high), IRQx informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. IRQx is generated when one or all of the above conditions occur and the value of bits 0 – 3 in the interrupt request level (0 ×70) is equal to x (of IRQx). The output drive sinks 24 mA at 0.4 V and sources 12 mA at 2.4 V. PNPBYPASS 66 I Bypass PnP configuration sequence. When PNPBYPASS is tied to GND, the PnP autoconfiguration sequence is bypassed. PNPS1 – PNPS0 52 – 53 O PnP internal states. See the PNPS1 and PNPS0 truth table in the PnP states section of this document. RESETDRV 45 I Reset. When active (high), RESETDRV clears most ACE registers and puts the ACE in wait for key state. The CSN is reset to 0 ×00. All configuration registers are set to their power-up values. |
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