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TPA0112PWP Folha de dados(PDF) 3 Page - Texas Instruments |
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TPA0112PWP Folha de dados(HTML) 3 Page - Texas Instruments |
3 / 34 page TPA0112 2-W STEREO AUDIO POWER AMPLIFIER WITH FOUR SELECTABLE GAIN SETTINGS SLOS204B – MAY 1999 – REVISED MARCH 2000 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 AVAILABLE OPTIONS PACKAGED DEVICE TA TSSOP† (PWP) –40 °C to 85°C TPA0112PWP † The PWP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g., TPA0112PWPR). Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION BYPASS 11 Tap to voltage divider for internal mid-supply bias generator GAIN0 2 I Bit 0 of gain control GAIN1 3 I Bit 1 of gain control GND 1, 12, 13, 24 Ground connection for circuitry. Connected to the thermal pad. LHPIN 6 I Left channel headphone input, selected when SE/BTL is held high LIN 10 I Common left input for fully differential input. AC ground for single-ended inputs. LLINEIN 5 I Left channel line input, selected when SE/BTL is held low LOUT+ 4 O Left channel positive output in BTL mode and positive output in SE mode LOUT– 9 O Left channel negative output in BTL mode and high-impedance in SE mode PC-BEEP 14 I The input for PC Beep mode. PC-BEEP is enabled when a > 1-V (peak-to-peak) square wave is input to PC-BEEP or PCB ENABLE is high. PCB ENABLE 17 I If this terminal is high, the detection circuitry for PC-BEEP is overridden and passes PC-BEEP through the amplifier, regardless of its amplitude. If PCB ENABLE is floating or low, the amplifier continues to operate normally. PVDD 7, 18 I Power supply for output stage RHPIN 20 I Right channel headphone input, selected when SE/BTL is held high RIN 8 I Common right input for fully differential input. AC ground for single-ended inputs. RLINEIN 23 I Right channel line input, selected when SE/BTL is held low ROUT+ 21 O Right channel positive output in BTL mode and positive output in SE mode ROUT– 16 O Right channel negative output in BTL mode and high-impedance in SE mode SHUTDOWN 22 I Places entire IC in shutdown mode when held low, except PC-BEEP remains active SE/BTL 15 I Input MUX control input. When this terminal is held high, the LHPIN or RHPIN and SE output is selected. When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected. VDD 19 I Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest performance. |
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