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TPA2051D3YFFR Folha de dados(PDF) 6 Page - Texas Instruments |
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TPA2051D3YFFR Folha de dados(HTML) 6 Page - Texas Instruments |
6 / 33 page TIMING REQUIREMENTS SCL SDA tw(H) tw(L) tsu1 th1 SCL SDA th2 t(buf) tsu2 tsu3 StartCondition StopCondition TPA2051D3 SLOS641 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com For I 2C Interface Signals and voltage power up sequence, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCL Frequency, SCL No wait states 400 kHz tW(H) Pulse duration, SCL high 0.6 µs tW(L) Pulse duration, SCL low 1.3 µs tsu1 Setup time, SDA to SCL 100 ns th1 Hold time, SCL to SDA 10 ns t(buf) Bus free time between stop and start condition 1.3 µs tsu2 Setup time, SCL to start condition 0.6 µs th2 Hold time, start condition to SCL 0.6 µs tsu3 Setup time, SCL to stop condition 0.6 µs tpws Power up delay time, AVDD and PVDD to DVDD 100 µs power up sequence tens Enable pin wait time 1000 µs tSWS SWS enable wait time 250 µs tEN Spk_Enable, HPL_Enable, HPR_Enable wait time 250 µs Figure 1. SCL and SDA Timing Figure 2. Start and Stop Conditions Timing 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPA2051D3 |
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Descrição semelhante - TPA2051D3YFFR |
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