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ISL28233FUZ Folha de dados(PDF) 10 Page - Intersil Corporation

Nome de Peças ISL28233FUZ
Descrição Electrónicos  Single, Dual, and Quad Micropower, Zero-Drift, RRIO Operational Amplifiers
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL28233FUZ Folha de dados(HTML) 10 Page - Intersil Corporation

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10
FN6560.1
May 29, 2009
Applications Information
Functional Description
The ISL28133 uses a proprietary auto-zero architecture
(Figure 34) that combines a 400kHz main amplifier with a
very high open loop gain (200dB) chopper stabilized
amplifier to achieve very low offset voltage and drift (2µV,
0.02µV/°C typical) while consuming only 18µA of supply
current per channel.
This multi-path amplifier architecture contains a time
continuous main amplifier whose input DC offset is corrected
by a parallel-connected, high gain chopper stabilized DC
correction amplifier operating at 100kHz. From DC to ~5kHz,
both amplifiers are active with DC offset correction and most
of the low frequency gain is provided by the chopper
amplifier. A 5kHz crossover filter cuts off the low frequency
amplifier path leaving the main amplifier active out to the
400kHz gain-bandwidth product of the device.
The key benefits of this architecture for precision
applications are very high open loop gain, very low DC
offset, and low 1/f noise. The noise is virtually flat across the
frequency range from a few millihertz out to 100kHz, except
for the narrow noise peak at the amplifier crossover
frequency (5kHz).
Rail-to-rail Input and Output (RRIO)
The RRIO CMOS amplifier uses parallel input PMOS and
NMOS that enable the inputs to swing 100mV beyond either
supply rail. The inverting and non-inverting inputs do not
have back-to-back input clamp diodes and are capable of
maintaining high input impedance at high differential input
voltages. This is effective in eliminating output distortion
caused by high slew-rate input signals.
The output stage uses common source connected PMOS
and NMOS devices to achieve rail-to-rail output drive
capability with 17mA current limit and the capability to swing
to within 20mV of either rail while driving a 10k
Ω load.
IN+ and IN- Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. For applications
where either input is expected to exceed the rails by 0.5V, an
external series resistor must be used to ensure the input
currents never exceed 20mA (Figure 35).
Layout Guidelines for High Impedance Inputs
To achieve the maximum performance of the high input
impedance and low offset voltage of the ISL28X33 amplifiers,
care should be taken in the circuit board layout. The PC board
surface must remain clean and free of moisture to avoid
leakage currents between adjacent traces. Surface coating of
the circuit board will reduce surface moisture and provide a
humidity barrier, reducing parasitic resistance on the board.
The use of guard rings around the amplifier inputs will further
reduce leakage currents. Figure 36 shows how the guard ring
should be configured. The guard ring does not need to be a
specific width, but it should form a continuous loop around
both inputs. By setting the guard ring voltage equal to the
voltage at the non-inverting input, parasitic capacitance is
minimized as well.
High Gain, Precision DC Coupled Amplifier
The circuit in Figure 37 implements a single-stage DC
coupled amplifier with an input DC sensitivity of under 100nV
that is only possible using a low VOS amplifier with high
open loop gain. High gain DC amplifiers operating from low
FIGURE 34. ISL28x33 FUNCTIONAL BLOCK DIAGRAM
VOUT
IN-
IN+
5kHz CROSSOVER
FILTER
CHOPPER STABILIZED DC OFFSET CORRECTION
MAIN AMPLIFIER
FIGURE 35. INPUT CURRENT LIMITING
-
+
RIN
RL
VIN
VOUT
ISL28133
IN
V+
FIGURE 36. USE OF GUARD RINGS TO REDUCE LEAKAGE
HIGH IMPEDANCE INPUT
GUARD RING
PC TRACE
+
-
ISL28133, ISL28233, ISL28433


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