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MC-45D32DA721KF-C75 Folha de dados(PDF) 8 Page - Elpida Memory |
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MC-45D32DA721KF-C75 Folha de dados(HTML) 8 Page - Elpida Memory |
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8 / 16 page  Preliminary Data Sheet E0037N10 8 Synchronous Characteristics Parameter Symbol -C75 (PC266B) -C80 (PC200) Unit Note MIN. MAX. MIN. MAX. Clock cycle time CL = 2.5 tCK 7.5 15 8 15 ns CL = 2 10 15 10 15 CLK high-level width tCH 0.45 0.55 0.45 0.55 tCK CLK low-level width tCL 0.45 0.55 0.45 0.55 tCK DQ output access time from CLK, /CLK tAC –0.75 0.75 –0.8 0.8 ns DQS output access time from CLK, /CLK tDQSCK –0.75 0.75 –0.8 0.8 ns DQS-DQ skew (for DQS and associated DQ signals) tDQSQ –0.5 0.5 –0.6 0.6 ns DQS-DQ skew (for DQS and all DQ signals) tDQSQA –0.5 0.5 –0.6 0.6 ns Data out low-impedance time from CLK, /CLK tLZ –0.75 0.75 –0.8 0.8 ns Data out high-impedance time from CLK, /CLK tHZ –0.75 0.75 –0.8 0.8 ns Half clock period tHP tCH, tCL tCH, tCL ns DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP – 0.75 tHP – 1 ns DQ and DM input setup time tDS 0.5 0.6 ns DQ and DM input hold time tDH 0.5 0.6 ns DQ and DM input pulse width (for each input) tDIPW 1.75 2 ns DQS write preamble setup time tWPRES 0 0 ns DQS write preamble tWPRE 0.25 0.25 tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK DQS input high pulse width tDQSH 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 tCK DQS falling edge to CLK setup time tDSS 0.2 0.2 tCK DQS falling edge hold time from CLK tDSH 0.2 0.2 tCK Address and control input setup time tIS 0.9 1.1 ns Address and control input hold time tIH 0.9 1.1 ns Address and control input pulse width tIPW 2.2 2.5 ns Internal write to read command delay tWTR 1 1 tCK Remark These specifications are applied to the monolithic device. |
Nº de peça semelhante - MC-45D32DA721KF-C75 |
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Descrição semelhante - MC-45D32DA721KF-C75 |
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