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MC-458CA726EFB-A10 Folha de dados(PDF) 1 Page - Elpida Memory |
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MC-458CA726EFB-A10 Folha de dados(HTML) 1 Page - Elpida Memory |
1 / 16 page The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. MOS INTEGRATED CIRCUIT MC-458CA726 8M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE DATA SHEET Document No. E0061N10 (1st edition) (Previous No. M13050EJ7V0DS00) Date Published January 2001 CP (K) Printed in Japan Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. Description The MC-458CA726EFB and MC-458CA726PFB are 8,388,608 words by 72 bits synchronous dynamic RAM module on which 5 pieces of 128M SDRAM : µPD45128163 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features • 8,388,608 words by 72 bits organization (ECC Type) • Clock frequency and access time from CLK Part number /CAS latency Clock frequency Access time from CLK (MAX.) (MAX.) MC-458CA726EFB-A80 CL = 3 125 MHz 6 ns CL = 2 100 MHz 6 ns MC-458CA726EFB-A10 CL = 3 100 MHz 6 ns CL = 2 77 MHz 7 ns MC-458CA726PFB-A80 CL = 3 125 MHz 6 ns CL = 2 100 MHz 6 ns MC-458CA726PFB-A10 CL = 3 100 MHz 6 ns CL = 2 77 MHz 7 ns • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle • Quad internal banks controlled by BA0 and BA1 (Bank Select) • Programmable burst-length (1, 2, 4, 8 and full page) • Programmable wrap sequence (sequential / interleave) • Programmable /CAS latency (2, 3) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • All DQs have 10 Ω ± 10 % of series resistor • Single 3.3 V ± 0.3 V power supply • LVTTL compatible • 4,096 refresh cycles /64 ms • Burst termination by Burst Stop command and Precharge command • 168-pin dual in-line memory module (Pin pitch = 1.27 mm) • Unbuffered type • Serial PD This product became EOL in September, 2002. |
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