6

4151N–AERO–04/09

M65608E

AC Parameters

AC Test Conditions

AC Test Loads Waveforms

Data Retention Mode

Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and sup-

ply current are guaranteed over temperature. The following rules ensure data retention:

1. During data retention chip select CS1 must be held high within VCC to VCC -0.2V or,

chip select CS2 must be held down within GND to GND +0.2V.

2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, mini-

mizing power dissipation.

3. During power up and power-down transitions CS1 and OE must be kept between VCC +

0.3V and 70% of VCC, or with CS2 between GND and GND -0.3V.

4. The RAM can begin operation > TR ns after VCC reaches the minimum operation volt-

ages (4.5V).

Timing

Input Pulse Levels: ....................................GND to 3.0V

Input Rise/Fall Times: ...............................5 ns

Input Timing Reference Levels: ................1.5V

Output loading IOL/IOH (see Figure 1 and Figure 2)+30 pF

Figure 1

Figure 2

Figure 3