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ST20P18 Folha de dados(PDF) 7 Page - Sitronix Technology Co., Ltd. |
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ST20P18 Folha de dados(HTML) 7 Page - Sitronix Technology Co., Ltd. |
7 / 12 page ST20P18 Ver 1.4 7/12 6/13/07 TABLE 6-2: Option ward TABLE 6-3: OTP option ward read back window 7 7.. P Po ow we err O On n T Tiim me err The Power-on Timer (PWRT) is offered necessary delays on power-up to keep the chip in reset until the crystal oscillator is stable, the typical delay time in 3v at 25℃ is 32ms, and operation in voltage 2.4V~5.5V ,60℃~ -10℃ is 4~640ms. The default state is high with one internal pull-up resistance. TABLE 7-4: Power on timer pin option Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default CP - - - WDTSTP WDTEN - PD 1--- 11-1 Bit 7: CP: OTP ROM code protect. 0 =protect OTP data. 1 =Un-Protect OTP data. Bit 3: WDTSTP: WDT stop control bit. 0 = WDT stop at WAI-1 and STP mode. 1 = WDT is always active if WDTEN is enabled. Bit 2: WDTEN: WDT enable. 0 = WDT disable. 1 = WDT enable. Bit 0: PD: Port function selection 0 = PD used as input port. 1 = OSC input pin for 32768Hz crystal. Address Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default $037 OPT R CP - - PWRT WDTSTP WDTEN - PD 1--1 11-1 IC pad option Description Default 0 disable power-on timer, tie to GND PWRT 1 enable power-on timer, tie to VCC 1:input pull-up |
Nº de peça semelhante - ST20P18 |
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Descrição semelhante - ST20P18 |
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