ST

ST2204

PRELIMINARY

8 BIT Integrated Microcontroller with 512K Bytes ROM

Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification.

Some parameters are subject to change.

Ver 0.6

1

2008/11/10

1

S

Totally static 8-bit CPU

ROM: 512K x 8-bit

RAM: 10K x 8-bit

Stack: Up to 128-level deep

Operation voltage: 2.4V ~ 3.6V

Operation frequency:

– 6.0Mhz@2.4V(Min.)

Low Voltage Detector (LVD)

Low Voltage Reset (LVR)

Memory interface to ROM, RAM, Flash

Memory configuration

– Three kinds of bank for program, data and interrupts

– 12-bit bank register supports up to 44M bytes

– 6 programmable chip-selects with 4 modes

General-Purpose I/O (GPIO) ports

– 48 multiplexed CMOS bidirectional bit programmable

I/Os

– Hardware de-bounce option for Port-A

– Bit programmable pull-up for input pins

– Bit programmable pull-up/down and open-drain/CMOS

for Port-C

Programmable Watchdog Timer (WDT)

Timer/Counter

– Two 8-bit timer, one can be a 16-bit event counter

– One 8-bit Base timer with 5 coexistent interrupt time

settings

Three clocking outputs

– Clock sources including Timer0/1, baud rate generator

11 prioritized interrupts with dedicated exception

vectors

– External interrupt (edge triggered)

– TIMER0 interrupt

– TIMER1 interrupt

– BASE timer interrupt

– PORTA interrupt (transition triggered)

– DAC reload interrupt

– LCD buffer interrupt

– SPI interrupt (x2)

– UART interrupts (x2)

Dual clock sources with warm-up timer

– Low frequency crystal oscillator (OSCX)

··················································· 32768 Hz

– RC oscillator (OSC) ·······························500K ~ 4M Hz

– High frequency crystal/resonator oscillator

(Bonding option)······455K~4M Hz

Direct Memory Access (DMA)

– Block-to-Block transfer

– Block to Single port

LCD Controller (LCDC)

– Software programmable screen size up to 320X240

– Support 1-, 4-bit LCD data bus

– Share system memory with display memory

– Large display area with small internal RAM buffer is

possible to free more internal RAM for temporary access

– Unique internal bus for memory sharing with no loss of

the CPU time

– Diverse functions including virtual screen, panning,

scrolling, contrast control and alternating signal

generator

– Gray level support: Hardware 4 levels/Software 31 levels

Universal Asynchronous Receiver/Transmitter (UART)

– Full-duplex operation

– Baud rate generator with one digital PLL

– Standard baud rates of 600 bps to 115.2 kbps

– Direct glueless support of IrDA physical layer protocol

– Two sets of I/Os (TX,RX) for two independent devices

Serial Peripheral Interface (SPI)

– Master and slave modes

– 5 serial signals including enable and data-ready

– One stage buffer for transmitter and receiver for

continuous data exchange

– Programmable data length from 7-bit to 16-bit

Programmable Sound Generator (PSG)

– Two channels with three playing modes

– Tone/noise generator

– 16-level volume control

– 8-bit PWM DAC for speech/voice

– Two dedicated outputs for directly driving and large

current

Three power down modes

– WAI0 mode

– WAI1 mode

– STP mode