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ADRF6601 Folha de dados(PDF) 8 Page - Analog Devices

Nome de Peças ADRF6601
Descrição Electrónicos  750 MHz to 1160 MHz Rx Mixer with Integrated Fractional-N PLL and VCO
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ADRF6601
Rev. 0 | Page 8 of 24
Pin No.
Mnemonic
Description
27
VCC_V2I
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.
29
IP3SET
Connect a resistor from this pin to a +5 V supply to adjust IIP3. Normally leave open.
32, 33
NC
No Connection.
36
LODRV_EN
LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON
pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is
set high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN pin
or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. The external LO drive frequency
must be 1× LO. This pin should not be left floating.
37, 38
LON, LOP
Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO
generation is disabled, an external 1× LO can be applied to these pins.
39
VTUNE
VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range
on this pin is 1.5 V to 2.5 V.
40
DECLVCO
Decoupling Node for the VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and
ground.
EP
EPAD
Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.


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