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74LVC16244A Folha de dados(PDF) 9 Page - NXP Semiconductors |
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74LVC16244A Folha de dados(HTML) 9 Page - NXP Semiconductors |
9 / 19 page 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 9 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state [1] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [2] Typical values are measured at Tamb =25 °C and VCC = 3.3 V. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(C L × VCC 2 × f o) = sum of the outputs. 11. Waveforms CPD power dissipation capacitance per buffer; VI =GND to VCC; VCC = 3.3 V [3] outputs enabled - 12 - - - pF outputs disabled - 4.0 - - - pF Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The input (nAn) to output (nYn) propagation delays mna171 nAn input nYn output tPLH tPHL GND VI VM VM VM VM VOH VOL |
Nº de peça semelhante - 74LVC16244A |
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Descrição semelhante - 74LVC16244A |
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