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CS1600-FSZ Folha de dados(PDF) 2 Page - Cirrus Logic |
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CS1600-FSZ Folha de dados(HTML) 2 Page - Cirrus Logic |
2 / 18 page CS1600 2 DS904A6 1. PIN DESCRIPTIONS Table 1. Pin Descriptions Pin Name Pin # I/O Description NC 1, 8 - No Connect — Connect these pins to VDD to prevent any leakage path that could arise from leaving them unterminated. STBY 2IN Standby — This is an active-low pin. Shorting this pin to GND disables PFC switch- ing. The input has a pull-up resistor and should be driven with an open-collector device. Leave this pin unterminated when not in use. IAC 3IN Rectified Line Voltage Sense — The IAC pin is used to sense the rectified line volt- age. This signal, in conjunction with the signal on the FB pin, is used in the Power Factor Correction (PFC) algorithm A filter capacitor of up to 2.2 nF may be added between this pin and VDD to provide noise immunity. FB 4IN Feedback Voltage Sense — The FB pin is used to sense the output voltage of the PFC stage. This signal, in conjunction with the signal on the IAC pin, is used in the Power Factor Correction (PFC) algorithm. A filter capacitor of up to 2.2 nF may be added between this pin and VDD to provide noise immunity. GND 5– Ground — GND is a common reference for all the functional blocks in this device. GD 6OUT Gate Drive — GD is the output of the device with a source capability of 0.5 A and a current sink capacity of 1 A. VDD 7IN IC Supply Voltage — VDD is the input used to provide bias to the device. This pin has an internal shunt to ground. An external bias needs to be applied for steady- state operation. A low-ESR ceramic decoupling capacitor at this pin is recommended for reliable operation of this device. NC STBY IAC FB NC VDD GD GND 1 2 3 4 8 7 6 5 |
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