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TS12A44515PWR Folha de dados(PDF) 8 Page - Texas Instruments |
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TS12A44515PWR Folha de dados(HTML) 8 Page - Texas Instruments |
8 / 16 page APPLICATION INFORMATION Power-Supply Considerations Logic-Level Thresholds High-Frequency Performance Test Circuits/Timing Diagrams TS12A44514 GND IN NO COM 50 Ω ∆VOUT isthemeasuredvoltagedueto charge transfer errorQwhenthechannelturnsoff. Q= VOUT xCL VIN VOUT VNO or VNC =0 V CL 1000 pF VIN VOUT ∆VOUT V+ V+ V+ 0 V TS12A44515 TS12A44514 TS12A44513 TS12A44515 TS12A44513 ,, TS12A44514,, TS12A44515 SCDS247 – OCTOBER 2008 ............................................................................................................................................................................................. www.ti.com The TS12A44513/TS12A44514/TS12A44515 construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Reverse ESD-protection diodes connected in series are internally connected between each analog-signal pin and both V+ and GND. If an analog signal exceeds V+ or GND, one of the diodes will be forward biased, but the other will be reverse biased preventing current flow. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog-signal paths and V+ or GND. V+ and GND also power the internal logic and logic-level translators. The logic-level translators convert the logic levels to switched V+ and GND signals to drive the analog signal gates. The logic-level thresholds are CMOS/TTL compatible when V+ is 5 V. As V+ is raised, the level threshold increases slightly. When V+ reaches 12 V, the level threshold is about 3 V – above the TTL-specified high-level minimum of 2.8 V, but still compatible with CMOS outputs. CAUTION: Do not connect the TS12A44513/TS12A44514/MAS4515 V+ to 3 V and then connect the logic-level pins to logic-level signals that operate from 5-V supply. Output levels can exceed 3 V and violate the absolute maximum ratings, damaging the part and/or external circuits. In 50- Ω systems, signal response is reasonably flat up to 250 MHz (see Typical Operating Characteristics). Above 20 MHz, the on response has several minor peaks that are highly layout dependent. The problem is not in turning the switch on; it is turning it off. The OFF-state switch acts like a capacitor and passes higher frequencies with less attenuation. At 10 MHz, OFF isolation is about –45 dB in 50- Ω systems, decreasing (approximately 20 dB per decade) as frequency increases. Higher circuit impedances also make OFF isolation decrease. OFF isolation is about 3 dB above that of a bare IC socket, and is due entirely to capacitive coupling. Figure 5. Charge Injection 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TS12A44513 TS12A44514 TS12A44515 |
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