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LC78628E Folha de dados(PDF) 11 Page - Sanyo Semicon Device |
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LC78628E Folha de dados(HTML) 11 Page - Sanyo Semicon Device |
11 / 40 page No. 6329-11/40 LC78628E Internal Functions 1. HF signal input circuit — Pin 11: EFMIN, pin 10: EFMO, pin 1: DEFI, pin 13: CLV+ When an HF signal is input to the EFMIN pin, an EFM signal (NRZ) sliced at the optimal level is acquired. As a measure to handle defects, when the DEFI pin (pin 1) goes high, the slice level controller output from the EFMO pin (pin 10) goes to the high-impedance state, and the slice level is held. However, this is only valid when the CLV circuit is in phase control mode, that is, when the V/P pin (pin 15) is outputting a low level. This function can be implemented in combination with the DEF pin from an LA9230/9240 series product. *: If the EFMIN and CLV+ lines are run close together, the error rate may increase due to spurious radiation. We recommend inserting either a ground or VDD shield line between these lines. 2. PLL clock regeneration circuit — Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK The LC78628E includes a built-in VCO circuit, and a PLL circuit is formed by adding external resistors and capacitors. The ISET pin sets the charge pump reference current, PDO sets the VCO circuit loop filter, and FR sets the VCO frequency range. Sample values for reference purposes: R1 = 68 k Ω, C1 = 0.1 µF R2 = 680 Ω, C2 = 0.1 µF R3 = 1.2 k Ω + – SLC SLI VREF 11 10 EFMIN EFMO HF signal A12803 VDD R1 C2 R2 R3 C1 5 ISET EFM(NRZ) PDO FR PCK VCO 1/N Charge pump Frequency and phase comparator 3 21 7 A12804 Code Command Frequency divisor RES = low $AC VCO × 2 SET 1 $AD VCO × 1 SET 2 $AE VCO × 0.5 SET 0.5 q q The divisor used by the divider to create PCK from the VCO can be set using the VCO × 2, VCO × 1, and VCO × 0.5 SET instructions. Normally, the circuit operates in the VCO × 0.5 SET state after a reset. |
Nº de peça semelhante - LC78628E |
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Descrição semelhante - LC78628E |
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