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ISL24202IRTZ-EVALZ Folha de dados(PDF) 2 Page - Intersil Corporation

Nome de Peças ISL24202IRTZ-EVALZ
Descrição Electrónicos  Programmable VCOM Calibrator with EEPROM
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL24202IRTZ-EVALZ Folha de dados(HTML) 2 Page - Intersil Corporation

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ISL24202
2
FN7587.0
March 15, 2011
Block Diagram
Pin Descriptions
Pin Configuration
ISL24202
(8 LD TDFN)
TOP VIEW
FIGURE 2. BLOCK DIAGRAM OF THE ISL24202
GND
DIGITAL
INTERFACE
DAC
REGISTERS
8-BIT EEPROM
CTL
DNC
CE
AVDD
SET
8
2
6
7
4
CS
OUT
1
Q1
A1
ANALOG DCP
AND
CURRENT SINK
UP/DOWN
COUNTER
5
VDD
3
VDD
RBIAS
RBIAS
PIN NAME PIN #
FUNCTION
OUT
1
Adjustable Sink Current Output Pin. The sink current into
the OUT pin is equal to the DAC setting times the
maximum adjustable sink current divided by 256. See
the “SET” pin function description below (pin 8) for
setting the maximum adjustable sink current.
AVDD
2
High-Voltage Analog Supply. Bypass to GND with 0.1µF
capacitor.
DNC
3
Do Not Connect to external circuitry. It is acceptable to
ground this pin.
GND
4
Ground connection.
VDD
5
Digital power supply input. Bypass to GND with 0.1µF
de-coupling capacitor.
CTL
6
Up/Down Control for internal counter and Internal
EEPROM Programming Control Input. When CE is high:
A low-to-mid transition increments the 8-bit counter,
adding 1 to the DAC setting, increasing the OUT sink
current, and lowering the divider voltage at the OUT pin.
A high-to-mid transition decrements the 8-bit counter,
subtracting 1 from the DAC setting, decreasing the OUT
sink current, and increasing the divider voltage at the
OUT pin.
To program the EEPROM, take this pin to >4.9V (see
“CTL EEPROM Programming Signal Time” in the
“Electrical Specifications” table on page 5 for details).
Float when not in use.
CE
7
Counter Enable Pin. Connect CE to VDD to enable
adjustment of the output sink current. Float or connect
CE to GND to prevent further adjustment or
programming (Note: the CE pin has an internal 500nA
pull-down sink current). The EEPROM value will be
copied to the register on a VOH to VOL transition.
SET
8
Maximum Sink Current Adjustment Pin. Connect a
resistor from SET to GND to set the maximum
adjustable sink current of the OUT pin. The maximum
adjustable sink current is equal to (AVDD/20) divided
by RSET.
PAD
-
Thermal pad should be connected to system ground
plane to optimize thermal performance.
(*CONNECT THERMAL PAD TO GND)
OUT
AVDD
DNC
GND
1
2
3
4
8
7
6
5
SET
CE
CTL
VDD
PAD


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