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FFPF10H60S Folha de dados(PDF) 4 Page - Fairchild Semiconductor |
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FFPF10H60S Folha de dados(HTML) 4 Page - Fairchild Semiconductor |
4 / 15 page AN-6982 APPLICATION NOTE © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.0 • 6/8/10 4 Figure 8. VRMS According to the PFC Operation Range Function To improve system efficiency at low AC line voltage and light load condition, FAN6982 provides two-level PFC output voltage. As shown in Figure 9, FAN6982 monitors VEA and VRMS voltages to adjust the PFC output voltage. When VEA and VRMS are lower than the thresholds, an internal current source of 20 µA is enabled and flows through RFB2, increasing the voltage of the FBPFC pin. This causes the PFC output voltage to reduce when 20 µA is enabled, calculated as: 12 22 2 (2 5 20 ) + =× × FB FB OPFC FB FB RR V. - μAR R (5) It is typical to set the second boost output voltage as 340V~300V. Figure 9. Two-Level PFC Output Block Oscillator The internal oscillator frequency is determined by the timing resistor and capacitor on the RT/CT pin. The frequency of the internal oscillator is given by: 1 0.56 360 OSC TT T f R CC = ⋅⋅ + (6) Dead time for the PFC gate drive signal is determined by: 360 DEAD T tC = (7) Dead time should be smaller than 2% of the switching period to minimize line current distortion around the line zero crossing. The duty cycle is determined by comparing IEA voltage with the sawtooth waveform on the RT/CT pin. Note that FAN6982 employs leading-edge modulation and the duty cycle reduces as IEA voltage increases. Figure 10. Timing Diagram RDY Function The RDY function shown in Figure 11 is controlled by the voltage of FBPFC. When the voltage of FBPFC is over than 96% of 2.5V, the RDY pin is be connected to SGND. Meanwhile, the internal MOSFET is turned off and the RDY pin is floated when FBPFC pin voltage is lower than 46% of 2.5V. This is typically used to control the startup and shutdown of downstream converter by connecting and disconnecting supply voltage of the downstream converter as shown in Figure 11. Typically, a bypass capacitor is connected across the RDY pin and ground to minimize noise interference. Figure 11. RDY Application Circuit |
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