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BU2508FV Folha de dados(PDF) 2 Page - Rohm |
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BU2508FV Folha de dados(HTML) 2 Page - Rohm |
2 / 9 page BU2508FV,BU2507FV Technical Note 2/8 www.rohm.com 2011.08 - Rev.C © 2011 ROHM Co., Ltd. All rights reserved. ● Electrical Characteristics (Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, Ta=25℃) Parameter Symbol Limits Unit Conditions MIN. TYP. MAX. <Digital unit> Power source current ICC - 0.85 2.8 mA At CLK = 10MHz, IAO = 0uA Input leak current IILK -5 - 5 μA VIN=0 to VCC Input voltage L VIL - - 0.8 V - Input voltage H VIH 2.0 - - V - Output voltage L VOL 0 - 0.4 V IOL=2.5mA Output voltage H VOH 4.6 - 5 V IOH=-2.5mA <Analog unit> Consumption current IrefH - 4.5 7.5 mA Data condition : at maximum current - 2.0 3.4 mA (*1) D/A converter upper standard voltage setting range VrefH 3.0 - 5 V Outputs does not necessarily take a value in standard voltage setting range. Value that output may take is in the buffer amplifier output voltage range (VO). D/A converter lower standard voltage setting range VrefL 0 - 1.5 V Buffer amplifier output voltage range VO 0.1 - 4.9 V IO=±100μA 0.2 - 4.75 IO=±1.0mA Buffer amplifier output drive range IO -2 - 2 mA Upper side saturation voltage =0.35V (on full scale setting, current sourcing ) Lower side saturation voltage =0.23V (on zero scale setting, current sinking ) Precision Differential non-linearity error DNL -1.0 - 1.0 LSB VrefH =4.796V VrefL=0.7V VCC=5.5V (4mV/LSB) No load (IO = +0mA) Integral non-linearity error INL -3.5 - 3.5 Zero point error SZERO -25 - 25 mV Full scale error SFULL -25 - 25 Buffer amplifier output impedance RO - 5 15 Ω - Pull-up I/O internal resistance value Rup 12.5 25 37.5 kΩ Input voltage 0V (Resistance value changes according to voltage to be impressed.) *1: Value in the case where CH1 ~ CH4 are set to maximum current (after reset) ● Timing Characteristics (Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, Ta=25℃) Parameter Symbol Limits Unit Conditions MIN. TYP. MAX. Judgment level is 80% / 20% of VCC. Reset L pulse width tRTL 50 - - nS - Clock L pulse width tCKL 50 - - - Clock H pulse width tCKH 50 - - - Clock rise time tcr - - 50 - Clock fall time tcf - - 50 - Data setup time tDCH 20 - - - Data hold time tCHD 40 - - - Load setup time tCHL 50 - - - Load hold time tLDC 50 - - - Load H pulse width tLDH 50 - - - DA output settling time tLDD - 7 20 μS CL≦100pF, VO:0.5V⇔4.5V . Until output value deference from final value becomes 1/2LSB (note) LD signal is level triggered. When LD input is on H level, internal shift-register state is loaded to DAC control latch. Clock transition during LD=H is inhibited. CLK DI LD Output tCKL tcr tCKH tcf tDCH tCHD tCHL tLDH tLDC tLDD RESET tRTL |
Nº de peça semelhante - BU2508FV_11 |
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Descrição semelhante - BU2508FV_11 |
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